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Based on Chapter 10, p328 in textbook, DDR comment on p373
some review:
There are many simulation and design tools available for digital logic.
There are major commercial Electronic Design Automation, EDA, systems
for todays digital logic. Cadence is one of todays major suppliers and
UMBC has Cadence software available on GL computers.
Mentor Graphics, Synopsis and others provide large tool sets.
Altera and Xilinx are major providers of software for making custom
integrated circuits using Field Programmable Gate Arrays, FPGA.
www.altera.com
Altera has a downloadable student version.
www.xilinx.com
See video ZYNQ relates to DDR4
free download xilinx
The best WEB site to find free EDA tools is www.geda.seul.org
FPGA and other CAD information
You can get working chips from VHDL using synthesis tools.
No connecting wires between components.
One of the quickest ways to get chips is to use FPGA's,
Field Programmable Gate Arrays.
The two companies listed below provide the software and the
foundry for you to design your own integrated circuit chips:
www.altera.com
www.xilinx.com
Complete Computer Aided Design, CAD, packages are available from
companies such as Cadence, Mentor Graphics and Synopsis.
For projects for this section of CMPE 310 we will not be using Cadence VHDL
and Cadence Verilog that are available on linux.gl.umbc.edu.
You have probably had Verilog and will get VHDL in CS411.
Using Cadence VHDL on Linux.GL machines
First: You must have an account on a GL machine. Every student
and faculty should have this, you can use Lab ITE 375.
Either log in directly to linux.gl.umbc.edu or
Use:
ssh linux.gl.umbc.edu or log in at ITE 375
cd cmpe310 # or replace this with the directory you are using
Then do your own thing with Makefile for other VHDL files
Remember each time you log on to do simulations:
source vhdl_cshrc
make -f Makefile_vhdl1 # or do your own thing.
"Hello World sample programs in VHDL
As usual, learn a language by starting with a simple "hello" program:
VHDL hello.vhdl
hello.run used in simulation
hello_vhdl.out output of simulation
Note two major parts of a VHDL program:
The "entity" is the interface, and the "architecture" is the implementation.
hello circuits
-- hello.vhdl Just output to the screen
-- compile and run commands
-- ncvhdl -v93 hello.vhdl
-- ncelab -v93 hello:circuits
-- ncsim -batch -logfile hello_vhdl.out -input hello.run hello
entity hello is -- test bench (top level like "main")
end entity hello;
library STD;
use STD.textio.all; -- basic I/O
library IEEE;
use IEEE.std_logic_1164.all; -- basic logic types
use IEEE.std_logic_textio.all; -- I/O for logic types
architecture circuits of hello is -- where declarations are placed
subtype word_32 is std_logic_vector(31 downto 0);
signal four_32 : word_32 := x"00000004"; -- just four
signal counter : integer := 1; -- initialized counter
alias swrite is write [line, string, side, width] ;
begin -- where code is placed
my_print : process is
variable my_line : line; -- type 'line' comes from textio
begin
write(my_line, string'("Hello VHDL")); -- formatting
writeline(output, my_line); -- write to "output"
swrite(my_line, "four_32 = "); -- formatting with alias
hwrite(my_line, four_32); -- format type std_logic_vector as hex
swrite(my_line, " counter= ");
write(my_line, counter); -- format 'counter' as integer
swrite(my_line, " at time ");
write(my_line, now); -- format time
writeline(output, my_line); -- write to display
wait;
end process my_print;
end architecture circuits;
Verilog hello.v
hello_v.out output of simulation
// hello.v First Verilog program
// command to compile and run
// verilog -q -l hello_v.out hello.v
module hello;
reg [31:0] four_32;
integer counter;
initial
begin
four_32 = 32'b00000000000000000000000000000100;
counter = 1;
$display("Hello Verilog");
$display("%b", four_32);
$display("counter = %d", counter);
end
endmodule // hello
// output
// Hello Verilog
// 00000000000000000000000000000100
// counter = 1
Other Digital Logic Tool Links
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