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There are many simulation and design tools available for digital logic.
Some sections of CMSC 313 use Logisim a Java applet that can be run
from any WEB browser. Logisim is interactive and dynamic yet seems
limited in circuit complexity and timing accuracy. Learn more at
Logisim WEB page
There are major commercial Electronic Design Automation, EDA, systems
for todays digital logic. Cadence is one of todays major suppliers and
UMBC has Cadence software available on GL computers.
Mentor Graphics, Synopsis and others provide large tool sets.
Altera and Xilinx are major providers of software for making custom
integrated circuits using Field Programmable Gate Arrays, FPGA.
www.altera.com
Altera has a downloadable student version.
www.xilinx.com
A WEB site to find simulators on wikipedia
For projects for this section of CMSC 313 we will use Cadence VHDL
and Cadence Verilog that are available on linux.gl.umbc.edu.
Using Cadence VHDL on Linux.GL machines
First: You must have an account on a GL machine. Every student
and faculty should have this.
Either log in directly to linux.gl.umbc.edu or
Use:
ssh linux.gl.umbc.edu
csh # VHDL needs the C shell, not the Bash shell
cd cs313 # or replace this with the directory you are using
Next: Follow instructions exactly for VHDL.
To get cs313.tar file into your cs313 directory (on /afs i.e.
available on all GL machines.)
cp /afs/umbc.edu/users/s/q/squire/pub/download/cs313.tar .
tar -xvf cs313.tar # this makes subdirectory vhdl with files
cd vhdl
"edit cds.lib put your directory after $HOME/
for example $HOME/cs313/vhdl
DEFINE vhdl_lib $HOME/vhdl/vhdl_lib
source vhdl_cshrc
make
more add32_test.out
make clean # saves a lot of disk quota
Then do your own thing with Makefile for other VHDL files
Remember each time you log on to do simulations:
csh
cd cs313/vhdl/
source vhdl_cshrc
make # or do your own thing.
For Verilog, create a Makefile, make changes
cut and paste following command once
source /afs/umbc.edu/software/cadence/etc/setup_2008/cshrc.cadence
Makefile for Cadence Verilog-XL
all: hello.out
hello.out: hello.v
verilog -q -l hello.out hello.v
FPGA and other CAD information
You can get working chips from VHDL using synthesis tools.
One of the quickest ways to get chips is to use FPGA's,
Field Programmable Gate Arrays.
The two companies listed below provide the software and the
foundry for you to design your own integrated circuit chips:
www.altera.com
www.xilinx.com
Complete Computer Aided Design, CAD, packages are available from
companies such as Cadence, Mentor Graphics and Synopsis.
"Hello World sample programs
As usual, learn a language by starting with a simple "hello" program:
VHDL hello.vhdl
hello.run used in simulation
hello_vhdl.out output of simulation
Note two major parts of a VHDL program:
The "entity" is the interface, and the "architecture" is the implementation.
hello circuits
-- hello.vhdl Just output to the screen
-- compile and run commands
-- ncvhdl -v93 hello.vhdl
-- ncelab -v93 hello:circuits
-- ncsim -batch -logfile hello_vhdl.out -input hello.run hello
entity hello is -- test bench (top level like "main")
end entity hello;
library STD;
use STD.textio.all; -- basic I/O
library IEEE;
use IEEE.std_logic_1164.all; -- basic logic types
use IEEE.std_logic_textio.all; -- I/O for logic types
architecture circuits of hello is -- where declarations are placed
subtype word_32 is std_logic_vector(31 downto 0);
signal four_32 : word_32 := x"00000004"; -- just four
signal counter : integer := 1; -- initialized counter
alias swrite is write [line, string, side, width] ;
begin -- where code is placed
my_print : process is
variable my_line : line; -- type 'line' comes from textio
begin
write(my_line, string'("Hello VHDL")); -- formatting
writeline(output, my_line); -- write to "output"
swrite(my_line, "four_32 = "); -- formatting with alias
hwrite(my_line, four_32); -- format type std_logic_vector as hex
swrite(my_line, " counter= ");
write(my_line, counter); -- format 'counter' as integer
swrite(my_line, " at time ");
write(my_line, now); -- format time
writeline(output, my_line); -- write to display
wait;
end process my_print;
end architecture circuits;
Verilog hello.v
hello_v.out output of simulation
// hello.v First Verilog program
// command to compile and run
// verilog -q -l hello_v.out hello.v
module hello;
reg [31:0] four_32;
integer counter;
initial
begin
four_32 = 32'b00000000000000000000000000000100;
counter = 1;
$display("Hello Verilog");
$display("%b", four_32);
$display("counter = %d", counter);
end
endmodule // hello
// output
// Hello Verilog
// 00000000000000000000000000000100
// counter = 1
Truth Tables For possible use with homework 4
VHDL t_table4.vhdl
t_table4.run used in simulation
t_table4.out output of simulation
-- t_table4.vhdl
library STD;
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;
entity t_table4 is
end t_table4;
architecture circuits of t_table4 is
procedure v_print( title : string ) is
variable my_line : line;
begin
writeline(output, my_line); -- blank line
write(my_line, "a b c | d " & title);
writeline(output, my_line);
write(my_line, string'("-------+----"));
writeline(output, my_line);
end v_print;
procedure t_print(a : std_logic;
b : std_logic;
c : std_logic;
d : std_logic) is
variable my_line : line;
begin
write(my_line, a);
write(my_line, string'(" "));
write(my_line, b);
write(my_line, string'(" "));
write(my_line, c);
write(my_line, string'(" | "));
write(my_line, d);
writeline(output, my_line);
end t_print;
begin -- test of t_table4
driver: process -- serial code
variable a, b, c, d : std_logic;
variable my_line : LINE;
variable bits: std_logic_vector(1 downto 0) := ('1','0');
begin -- process driver
write(my_line, string'("Truth table."));
writeline(output, my_line);
v_print("d := not a and b and not c ;");
for i in 0 to 1 loop
a := bits(i);
for j in 0 to 1 loop
b := bits(j);
for k in 0 to 1 loop
c := bits(k);
d := not a and b and not c;
t_print(a, b, c, d);
end loop; -- c
end loop; -- b
end loop; -- a
wait for 2 ns;
end process driver;
end architecture circuits; -- of t_table4
ncsim: 06.11-s008: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
ncsim> run 2 ns
Truth table.
a b c | d d := not a and b and not c ;
-------+----
0 0 0 | 0
0 0 1 | 0
0 1 0 | 1
0 1 1 | 0
1 0 0 | 0
1 0 1 | 0
1 1 0 | 0
1 1 1 | 0
Ran until 2 NS + 0
ncsim> exit
Verilog t_table4.v
t_table4_v.out output of simulation
// t_table4.v
`timescale 1ns/1ns // set time unit and time lsb
module t_table4;
reg a, b, c, d;
integer i, j, k;
reg val[1:2];
initial
begin
val[1] = 0;
val[2] = 1;
$display("a b c | d = ~a*b*~c");
$display("------+---");
for(i=1; i<=2; i=i+1)
begin
a = val[i];
for(j=1; j<=2; j=j+1)
begin
b = val[j];
for(k=1; k<=2; k=k+1)
begin
c = val[k];
d = ~a*b*~c; // equation for truth table
$display("%b %b %b | %b", a, b, c, d);
end
end
end
end
endmodule
// output
a b c | d = ~a*b*~c
------+---
0 0 0 | 0
0 0 1 | 0
0 1 0 | 1
0 1 1 | 0
1 0 0 | 0
1 0 1 | 0
1 1 0 | 0
1 1 1 | 0
Other Digital Logic Tool Links
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