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Examples of Busses circa 2012 including older (changes with time)
Bus name Max Max Max width comment
Mbits MBytes MHz
per sec per sec
front side 17,024 2,128 133 128 many possible
34,048 4,256 133 256
19,200 2,400 150 128
85,248 10,656 333 256
136,448 17,056 533 256
204,800 25,600 800 256
225,280 26,160 880 256
256,000 32,000 1,000 256
320,000 40,000 1,250 256 (Mac G5)
AGP 2,112 264 66 32
AGP8X 17,056 2,132 533 32
PCI 1,056 132 33 32
PCI 2,112 264 33 64
PCI 2,112 264 66 32
PCI 4,224 528 66 64
PCI 4,224 528 133 32
PCI 8,448 1,056 133 64
PCIX 17,056 2,132 533 32 extended, compatible
PCIe 64,000 8,000 2000 32 express, one way, full duplex
1,2,4,8,12,16 or 32 lanes
ATA 100 800 100 25 32
ATA 133 1064 133 33 32
ATA 160 1280 160 40 32
SATA 150 1200 150 600 2 one way, full duplex
SATA std 1500 187 1500 1 one way, full duplex
limited by motherboard
SATA II 300 2400 300 1200 2
SATA II std 3000 375 3000 1 no forcing to build standard
SATA 3.0 6000 750 6000 1
SCSI 1 40 5 5 8
SCSI 2 160 20 10 16
SCSI 3 1280 160 80 16
SCSI UW3 2560 320 160 16
SCSI 320 5120 640 320 16 has cable terminators
Firewire1394 400 50 400 1
Firewire1394b 800 100 800 1 many video cameras
Firewire S16 1600 200 1600 1
Firewire S32 3200 400 3200 1
Firewire S80 6400 800 6400 1
USB 1.1 12 1.5 12 1 slow
USB 2 480 60 480 1 new cable
USB 3 3200 400 1600 2 new cable, dual differential
5000 625 2500 2 new connectors, optional speed
6400 800 3200 2 micro, mini, etc.
Fiberchannel 1000 125 1000 1 1062.5
Fiberchannel 2000 250 2000 1 >mile
Fibre 16GFC 3200 14000 full duplex 10Km
Fibre 20GFC 5100 21000 full duplex
Ethernet 10 10 1.25 10 1
Ethernet 100 100 12.5 100 1
Ethernet 1Gig 1000 125 1000 1
Ethernet 10G 10000 1,250 10000 1
ISA 400 50 25 16 really old
IEEE 1284 ECP 2.5 0.31 0.31 8 half duplex
printer port
V.90 56 0.056 0.005 0.056 1 modem, one way, full duplex
OC-48 2,500 optical cross country
OC-192 STM64 10,000 Optical Carrier
OC-768 STM256 40,000 5,000 light
Mbps MBps MHz
The speed of light limits the amount of information that can be
sent over a given distance. Many busses have length restrictions.
Light can travel about
300,000,000 meters per second
300,000 meters per millisecond
300 meters per microsecond
0.3 meters per nanosecond (about 1 foot)
0.3 millimeters per picosecond
Unchanged in last few decades. (slower inside integrated circuit)
Pentium 4 busses and PCI-X vs PCIe
Note one example of AGP being replaced by PCI-e and the mention
of many "busses" in the advertisement:
A non Intel architecture:
Below is a schematic of a one clock per instruction computer.
The operation for each instruction is:
The Instruction Pointer Register contains the address of the
next instruction to be executed.
The instruction address goes into the Instruction Memory of
Instruction Cache and the instruction comes out.
"inst" on the diagram.
The Instruction Decode has all the bytes of the instruction:
The instruction has bits for the operation code.
e.g. there is a different bit pattern for add, sub, etc.
Most instructions will reference one register. The register
number has enough bits to select one of the general registers.
Many instructions have a second register. (Not shown here,
on some computers there can be three registers.) The second
(or third) register may be the register number that receives
the result of the operation.
Many instructions have either a memory address for a operand or
a memory offset from a register or immediate data for use by
the operation. This data is passed into the ALU for use by
the operation, either for computing a result or computing
an address.
The general registers receive two register numbers and very
quickly output the data from those two registers.
The ALU receives two data values and control from the
Operation Code part of the instruction. The ALU computes
the value and outputs the value on the line labeled "addr".
This line goes three places: To the mux and possibly into
the Instruction Pointer if the operation is a jump or a branch.
To the Data Memory or Data Cache if the value is a computed
memory address. To the mux that may return the value to a register.
The Data Memory or Data Cache receives an address and write data.
Depending on the control signals "write" and "read":
The Data Memory reads the memory value and send it to the mux.
The Data Memory writes the "write date" into memory at
the memory location "addr".
The final mux may take a value just read from the Data Memory
or Data Cache and return that value to a register or
take the computed value from the ALU and return that value
to a register.
While the above signals are propagating, the Instruction Pointer
is updated by either incrementing by the number of bytes in the
instruction or from the jump or branch address.
This is one instruction, the clock transitions and the next instruction
is started.
The timing consideration that limits the speed of this design is
the long propagation from the new Instruction Pointer value until
the register is written. Notice that the register is written on
clock_bar and the Data Cache is written on clock_bar. Any real
computer must use instruction and data caches for this design
because RAM memory access is slower than logic on the CPU chip.
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