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Project part1 starts with part1_start.vhdl
Search for "???" where you need to do some work.
!!! remove ??? , ... , they are not legal VHDL.
WB_write_enb <= needs WB_lwop or WB_lwimop or ...
Above: RegDst WORK.equal6 ID_IR(31 downto 26) , "000000"
Similar for ALUSrc compare to "000000" get complement,
ALUSrc <= not complement
Below: need "not inB" signal, into WORK.mux_32 and new
output name that also goes into B side of ALU.
with ALU schematic for all, also see more on schematic below.
All include divide, divcas16 covered in Lecture 8 and provided.
Use your add32.vhdl from HW4.
Use your pmul16.vhdl from HW6.
Various versions have different signal names for same signal,
orop_and may be just orop, result of anding oropa with rrop
S_sel may be shortened name for sllop_or_srlop
S_sel <= sllop_and or srlop_and;
Remember from cs411_opcodes.txt, sll instruction has bottom
six bits "000010" and typical code would call that signal sllop.
But, many instructions could have those bottom bits, thus
to be sure the instruction is sll check top six bits, RRop,
equal to zero and call that signal sllop_and.
Similar for all instructions. Some schematics use a short hand,
just sllop meaning the instruction is an sll, yet VHDL code
needs sllop_and .
Extracted code to indicate where you need to do some work "...":
-- part1_start.vhdl VHDL '93 version using entities from WORK library
part1_start.vhdl to modify
library IEEE;
use IEEE.std_logic_1164.all;
entity alu_32 is -- given. Do not change this interface
port(inA : in std_logic_vector (31 downto 0);
inB : in std_logic_vector (31 downto 0);
inst : in std_logic_vector (31 downto 0);
result : out std_logic_vector (31 downto 0));
end entity alu_32;
architecture schematic of alu_32 is
signal cin : std_logic := '0';
signal cout : std_logic;
signal RRop : std_logic;
signal orop : std_logic;
signal orop_and : std_logic;
signal andop : std_logic;
signal andop_and : std_logic;
signal S_sel : std_logic;
-- ??? insert other needed signals
signal mulop : std_logic;
signal mulop_and : std_logic;
signal divop : std_logic;
signal divop_and : std_logic;
signal aresult : std_logic_vector (31 downto 0);
signal bresult : std_logic_vector (31 downto 0);
signal orresult : std_logic_vector (31 downto 0);
signal andresult : std_logic_vector (31 downto 0);
signal mulresult : std_logic_vector (31 downto 0);
signal divresult : std_logic_vector (31 downto 0);
signal divrem : std_logic_vector (31 downto 0);
begin -- schematic
--
-- REPLACE THIS SECTION FOR PROJECT PART 1
-- (add the signals you need above "begin"
--
ORR : entity WORK.equal6 port map(inst(31 downto 26), "000000", RRop);
Oor: entity WORK.equal6 port map(inst(5 downto 0), "001101", orop);
Omul: entity WORK.equal6 port map(inst(5 downto 0), "011011", mulop);
Odiv: entity WORK.equal6 port map(inst(5 downto 0), "011000", divop);
-- ??? insert other xxxop statements
orop_and <=orop and RRop;
mulop_and <=mulop and RRop;
divop_and <=divop and RRop;
-- ??? insert other xxx_and statements
adder: entity WORK.add32 port map(a => inA,
b => inB,
cin => cin,
sum => aresult,
cout => cout);
Mul: entity WORK.pmul16 port map(inA(15 downto 0),
inB(15 downto 0),
mulresult(31 downto 0));
Div: entity WORK.divcas16 port map(inA(31 downto 0),
inB(15 downto 0),
divresult(15 downto 0),
divrem(15 downto 0));
Omux: entity WORK.mux32_6 port map(in0=>aresult,
in1=>bresult,
in2=>andresult,
in3=>orresult,
in4=>mulresult,
in5=>divquo32,
ct1=>S_sel,
ct2=>andop_and,
ct3=>orop_and,
ct4=>mulop_and,
ct5=>divop_and,
result=>result);
end architecture schematic; -- of alu_32
... big cut
-- put additional debug print here, if needed, delete before submit
end architecture schematic; -- of part1_start
Do a final search for ???
Oh! You need to compute WB_RRop.
You know RRop is register to register operations add, sub, ...
that has 6 zeros in instruction bits 31 downto 0.
WB write back stage instruction is WB_IR.
WBrrop: entity WORK.equal6 port map( WB_IR(31 downto 26),"000000", WB_RRop);
similar statement for WB_addiop look up "------"
Of course, you need to define the signals WB_RRop and WB_addiop and
put the or ... inside the )
The additional files needed are:
part1.abs the program to be executed
part1.run to stop execution, no halt instruction
part1.chk the expected output
cs411_opcodes.txt opcode bit patterns
You will need to enter opcode bit patterns not in part1_start.vhdl.
Use Makefile_411 to compile and run your .vhdl with Cadence
Use Makefile_ghdl to compile and run your .vhdl with GHDL
Now, work on the ALU
The full project writeup:
cs411_proj.shtml
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