// tbmul8.e  a test circuit for bmul8
//           uses add8.e and bmul8.e components

// included is an 4 bit counter to test 16 cases

// counter4.e a 4 bit counter
// cntr[4] is the 4 bits to be counted
// clk is the system clock      (usually initialize to 1)
define counter4(cntr[4], clk)
circuits
  cntr[0] <= ~cntr[0] on falling clk;
  cntr[1] <= ~cntr[1] on falling cntr[0];
  cntr[2] <= ~cntr[2] on falling cntr[1];
  cntr[3] <= ~cntr[3] on falling cntr[2];
end circuits;
end counter4;


// main circuit to test the multiplier 
// checking is manual via  tbmul8.run

signal a[8]; // multiplier
signal b[8]; // multiplicand
signal c[16]; // product
signal clk <= #b1; // clock
signal cntr[4] <= #h0; // 4 bit counter to generate test cases
circuits
  clk <= ~clk after 50ns;  // the clock generator, period is 100ns
  cnt use counter4(cntr, clk);
  a <= cntr[1:0].#b000000;  // a few values for a
  b <= cntr[3:2].#b000000;  // a few values for b

  mul use bmul8(a, b, c);

end circuits;