// t_table.vhdl   try:  and, or, nand, nor, xor, xnor, not

`timescale 1ns/1ns // set time unit and time lsb
module t_table;
  reg a, b, c;
  integer i, j;
  reg val[1:4];
  initial
    begin
      val[1] = 0;
      val[2] = 1;
      val[3] = 1'b x;
      val[4] = 1'b z;
      $display("a b | c=a&b  and(c,a,b)");
      for(i=1; i<=4; i=i+1)
      begin
        a = val[i];
        for(j=1; j<=4; j=j+1)
        begin
          b = val[j];
          // and #1 my_and(c, a, b); circuit 
          c = a & b; // behavioral
          $display("%b %b | %b", a, b, c);
        end
      end

      $display("\na b | c=a|b  or(c,a,b)");
      for(i=1; i<=4; i=i+1)
      begin
        a = val[i];
        for(j=1; j<=4; j=j+1)
        begin
          b = val[j];
          // or #1 my_or(c, a, b); circuit 
          c = a | b; // behavioral
          $display("%b %b | %b", a, b, c);
        end
      end

      $display("\na b | c=a^b  xor(c,a,b)");
      for(i=1; i<=4; i=i+1)
      begin
        a = val[i];
        for(j=1; j<=4; j=j+1)
        begin
          b = val[j];
          // xor #1 my_xor(c, a, b); circuit 
          c = a ^ b; // behavioral
          $display("%b %b | %b", a, b, c);
        end
      end

      $display("\na | c=~a  not(c,a)");
      for(i=1; i<=4; i=i+1)
      begin
        a = val[i];
        // not #1 my_not(c, a); circuit 
          c = ~a; // behavioral
          $display("%b | %b", a, c);
      end

    end
endmodule