-- test add and subtract
-- sub4.vhdl    this could be three or more files

library IEEE;
use IEEE.std_logic_1164.all;

entity fadd is               -- full adder stage, interface
  port(a    : in  std_logic;
       b    : in  std_logic;
       cin  : in  std_logic;
       s    : out std_logic;
       cout : out std_logic);
end entity fadd;

architecture circuits of fadd is  -- full adder stage, body
begin  -- circuits of fadd
  s <= a xor b xor cin after 1 ns;
  cout <= (a and b) or (a and cin) or (b and cin) after 1 ns;
end architecture circuits; -- of fadd

library IEEE;
use IEEE.std_logic_1164.all;

entity add4 is               -- 4-bit adder
  port(a    : in  std_logic_vector(3 downto 0);
       b    : in  std_logic_vector(3 downto 0);
       cin  : in  std_logic;
       sum  : out std_logic_vector(3 downto 0);
       cout : out std_logic);
end entity add4;

architecture circuits of add4 is  -- 4-bit adder
  signal c : std_logic_vector(3 downto 0);  -- internal wires
begin  -- circuits of add4
  a0: entity WORK.fadd port map(a(0), b(0),  cin, sum(0), c(0));
  a1: entity WORK.fadd port map(a(1), b(1), c(0), sum(1), c(1));
  a2: entity WORK.fadd port map(a(2), b(2), c(1), sum(2), c(2));
  a3: entity WORK.fadd port map(a(3), b(3), c(2), sum(3), cout);
end architecture circuits; -- of add4

library IEEE;
use IEEE.std_logic_1164.all;

entity mux4 is
  port(in0    : in  std_logic_vector(3 downto 0);
       in1    : in  std_logic_vector(3 downto 0);
       ctl    : in  std_logic;
       result : out std_logic_vector(3 downto 0));
end entity mux4;

architecture behavior of mux4 is 
begin  -- behavior, using concurrent statement
  result <= in1 when ctl='1' else in0 after 250 ps;
end architecture behavior;  -- of mux4

use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;

entity sub4 is
end sub4;

architecture circuits of sub4 is
  signal subtract : std_logic := '0';     -- add or subtract
  signal a:      std_logic_vector(3 downto 0):=('0','1','0','0');
  signal b:      std_logic_vector(3 downto 0):=('0','0','1','0');
  signal sum:    std_logic_vector(3 downto 0);       
  signal cout :  std_logic;

  signal b_bar : std_logic_vector(3 downto 0);
  signal b_mux : std_logic_vector(3 downto 0);

  procedure print_values is       -- format output
    variable my_line : LINE;
  begin
    write(my_line, string'("subtract="));
    write(my_line, subtract);
    write(my_line, string'(", a="));
    write(my_line, a(3));
    write(my_line, a(2));
    write(my_line, a(1));
    write(my_line, a(0));
    write(my_line, string'(", b="));
    write(my_line, b(3));
    write(my_line, b(2));
    write(my_line, b(1));
    write(my_line, b(0));
    write(my_line, string'(", sum="));
    write(my_line, sum(3));
    write(my_line, sum(2));
    write(my_line, sum(1));
    write(my_line, sum(0));
    write(my_line, string'(", cout="));
    write(my_line, cout);
    writeline(output, my_line);
  end print_values;

begin  -- circuits of sub4
  a4: entity work.add4 port map(a, b_mux, subtract, sum, cout);
  i4: b_bar <= not b;
  m4: entity work.mux4 port map(b, b_bar, subtract, b_mux);

  driver: process                      -- serial code, test driver
            variable my_line : LINE;
          begin  -- process driver
            for i in 0 to 7 loop 
              if i mod 2 = 0 then
                subtract <= '0';
              else
                subtract <= '1';
              end if;
              case i is
                when 2 => a <= std_logic_vector' ('1','1','0','0');
                when 4 => b <= std_logic_vector' ('1','1','1','0');
                when 6 => a <= std_logic_vector' ('0','0','1','1');
                when others => null;
              end case;
              wait for 8 ns;         --  propagating signals
              print_values;            -- write output
            end loop;  -- i
            wait for 100 ns;
          end process driver;
end architecture circuits; -- of sub4