-- sqrt32_test.vhdl  test driver for sqrt32.vhdl (256 cases)

library STD;
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
--use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;

entity sqrt32_test is  -- test driver
end sqrt32_test;

architecture test of sqrt32_test is
  signal P : std_logic_vector(31 downto 0);
  signal U : std_logic_vector(15 downto 0);

  procedure print(P : std_logic_vector(31 downto 0);
                  U : std_logic_vector(15 downto 0)) is
    variable my_line : line;
    alias swrite is write [line, string, side, width] ;
  begin
    swrite(my_line, "sqrt( ");
    write(my_line, P);
    swrite(my_line, " )= ");
    write(my_line, U);
    writeline(output, my_line);
  end print;
  
begin  -- test of sqrt32_test
  s1: entity work.sqrt32  port map(P, U);    -- parallel code
  driver: process                      -- serial code
          begin  -- process driver
            for I in 0 to 255 loop
              P(31 downto 24) <= std_logic_vector(to_unsigned(I,8));
              P(23 downto 16) <= std_logic_vector(to_unsigned(I,8));
              P(15 downto  8) <= std_logic_vector(to_unsigned(I,8));
              P( 7 downto  0) <= std_logic_vector(to_unsigned(I,8));
              wait for 1 ns;
              print(P, U);
            end loop;
          end process driver;
end architecture test;   -- of sqrt32_test