-- sqrt16m.vhdl unsigned integer sqrt 16-bits computing unsigned integer 8-bits -- sqrt(0000000000000100) = 00000010 sqrt(4)=2 -- sqrt(0000000001000000) = 00001000 sqrt(64)=8 library IEEE; use IEEE.std_logic_1164.all; entity Sm is -- subtractor multiplexor port ( x : in std_logic; y : in std_logic; b : in std_logic; u : in std_logic; d : out std_logic; bo : out std_logic); end Sm; architecture circuits of Sm is signal t011, t111, t010, t001, t100, td : std_logic; begin -- circuits of Sm t011 <= (not x) and y and b; t111 <= x and y and b; t010 <= (not x) and y and (not b); t001 <= (not x) and (not y) and b; t100 <= x and (not y) and (not b); bo <= t011 or t111 or t010 or t001; td <= t100 or t001 or t010 or t111; d <= td when u='1' else x; end architecture circuits; -- of Sm library IEEE; use IEEE.std_logic_1164.all; entity Sb is port ( x : in std_logic; y : in std_logic; b : in std_logic; bo : out std_logic); end Sb; architecture circuits of Sb is signal t011, t111, t010, t001 : std_logic; begin -- circuits of Sb t011 <= (not x) and y and b; t111 <= x and y and b; t010 <= (not x) and y and (not b); t001 <= (not x) and (not y) and b; bo <= t011 or t111 or t010 or t001; end architecture circuits; -- of Sb library IEEE; use IEEE.std_logic_1164.all; entity S1 is -- subtractor multiplexor port ( x : in std_logic; b : in std_logic; u : in std_logic; d : out std_logic; bo : out std_logic); end S1; architecture circuits of S1 is signal t100, t001, td : std_logic; begin -- circuits of S1 t001 <= (not x) and b; t100 <= x and (not b); bo <= t001; td <= t100 or t001; d <= td when u='1' else x; end architecture circuits; -- of S1 library IEEE; use IEEE.std_logic_1164.all; entity S0 is port ( x : in std_logic; u : in std_logic; d : out std_logic; bo : out std_logic); end S0; architecture circuits of S0 is begin -- circuits of S0 bo <= not x; d <= not x when u='1' else x; end architecture circuits; -- of S0 library IEEE; use IEEE.std_logic_1164.all; entity Sn is -- subtractor multiplexor port ( x : in std_logic; b : in std_logic; bo : out std_logic); end Sn; architecture circuits of Sn is begin -- circuits of Sn bo <= (not x) nand b; -- complemented end architecture circuits; -- of Sn library IEEE; use IEEE.std_logic_1164.all; entity S0b is port ( x : in std_logic; bo : out std_logic); end S0b; architecture circuits of S0b is begin -- circuits of S0b bo <= not x; end architecture circuits; -- of S0b library IEEE; use IEEE.std_logic_1164.all; entity S1b is port ( x : in std_logic; b : in std_logic; bo : out std_logic); end S1b; architecture circuits of S1b is begin -- circuits of S1b bo <= (not x) and b; end architecture circuits; -- of S1b library IEEE; use IEEE.std_logic_1164.all; entity psqrt is port ( P : in std_logic_vector(15 downto 0); U : out std_logic_vector(7 downto 0)); end psqrt; architecture circuits of psqrt is signal b000, b001, b002, b003, b004, b005, b006, b007, b008, b009 : std_logic; signal x102, x103, x104, x105, x106, x107, x108, x109 : std_logic; signal b102, b103, b104, b105, b106, b107, b108, b109, b110 : std_logic; signal x204, x205, x206, x207, x208, x209, x210 : std_logic; signal b204, b205, b206, b207, b208, b209, b210, b211 : std_logic; signal x306, x307, x308, x309, x310, x311 : std_logic; signal b306, b307, b308, b309, b310, b311, b312 : std_logic; signal x408, x409, x410, x411, x412 : std_logic; signal b408, b409, b410, b411, b412, b413 : std_logic; signal x510, x511, x512, x513 : std_logic; signal b510, b511, b512, b513, b514 : std_logic; signal x612, x613, x614 : std_logic; signal b612, b613, b614, b615 : std_logic; signal x714, x715 : std_logic; signal b714, b715, bxx : std_logic; begin -- circuits of psqrt -- x y b u d bo s714: entity work.S0 port map(P(14), b715, x714, b714); s715: entity work.S1 port map(P(15), b714, b715, x715, bxx ); b715 <= not bxx; s612: entity work.S0 port map(P(12), b615, x612, b612); s613: entity work.S1 port map(P(13), b612, b615, x613, b613); s614: entity work.Sm port map(x714, b715, b613, b615, x614, b614); s615: entity work.Sn port map(x715, b614, b615); s510: entity work.S0 port map(P(10), b514, x510, b510); s511: entity work.S1 port map(P(11), b510, b514, x511, b511); s512: entity work.Sm port map(x612, b615, b511, b514, x512, b512); s513: entity work.Sm port map(x613, b715, b512, b514, x513, b513); s514: entity work.Sn port map(x614, b513, b514); s408: entity work.S0 port map(P(8), b413, x408, b408); s409: entity work.S1 port map(P(9), b408, b413, x409, b409); s410: entity work.Sm port map(x510, b514, b409, b413, x410, b410); s411: entity work.Sm port map(x511, b615, b410, b413, x411, b411); s412: entity work.Sm port map(x512, b715, b411, b413, x412, b412); s413: entity work.Sn port map(x513, b412, b413); s306: entity work.S0 port map(P(6), b312, x306, b306); s307: entity work.S1 port map(P(7), b306, b312, x307, b307); s308: entity work.Sm port map(x408, b413, b307, b312, x308, b308); s309: entity work.Sm port map(x409, b514, b308, b312, x309, b309); s310: entity work.Sm port map(x410, b615, b309, b312, x310, b310); s311: entity work.Sm port map(x411, b715, b310, b312, x311, b311); s312: entity work.Sn port map(x412, b311, b312); s204: entity work.S0 port map(P(4), b211, x204, b204); s205: entity work.S1 port map(P(5), b204, b211, x205, b205); s206: entity work.Sm port map(x306, b312, b205, b211, x206, b206); s207: entity work.Sm port map(x307, b413, b206, b211, x207, b207); s208: entity work.Sm port map(x308, b514, b207, b211, x208, b208); s209: entity work.Sm port map(x309, b615, b208, b211, x209, b209); s210: entity work.Sm port map(x310, b715, b209, b211, x210, b210); s211: entity work.Sn port map(x311, b210, b211); s102: entity work.S0 port map(P(2), b110, x102, b102); s103: entity work.S1 port map(P(3), b102, b110, x103, b103); s104: entity work.Sm port map(x204, b211, b103, b110, x104, b104); s105: entity work.Sm port map(x205, b312, b104, b110, x105, b105); s106: entity work.Sm port map(x206, b413, b105, b110, x106, b106); s107: entity work.Sm port map(x207, b514, b106, b110, x107, b107); s108: entity work.Sm port map(x208, b615, b107, b110, x108, b108); s109: entity work.Sm port map(x209, b715, b108, b110, x109, b109); s110: entity work.Sn port map(x210, b109, b110); s000: entity work.S0b port map(P(0), b000); s001: entity work.S1b port map(P(1), b000, b001); s002: entity work.Sb port map(x102, b110, b001, b002); s003: entity work.Sb port map(x103, b211, b002, b003); s004: entity work.Sb port map(x104, b312, b003, b004); s005: entity work.Sb port map(x105, b413, b004, b005); s006: entity work.Sb port map(x106, b514, b005, b006); s007: entity work.Sb port map(x107, b615, b006, b007); s008: entity work.Sb port map(x108, b715, b007, b008); s009: entity work.Sn port map(x109, b008, b009); U(0) <= b009; U(1) <= b110; U(2) <= b211; U(3) <= b312; U(4) <= b413; U(5) <= b514; U(6) <= b615; U(7) <= b715; end architecture circuits; -- of psqrt library STD; use STD.textio.all; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_textio.all; --use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; entity sqrt16m is -- test driver end sqrt16m; architecture test of sqrt16m is signal P : std_logic_vector(15 downto 0); signal U : std_logic_vector(7 downto 0); procedure print(P : std_logic_vector(15 downto 0); U : std_logic_vector(7 downto 0)) is variable my_line : line; alias swrite is write [line, string, side, width] ; begin swrite(my_line, "sqrt( "); write(my_line, P); swrite(my_line, " )= "); write(my_line, U); writeline(output, my_line); end print; begin -- test of sqrt16m s1: entity work.psqrt port map(P, U); -- parallel code driver: process -- serial code begin -- process driver for I in 0 to 255 loop P <= std_logic_vector(to_unsigned(I*I,16)); wait for 1 ns; print(P, U); end loop; end process driver; end architecture test; -- of sqrt16m