printout:  process(clk) -- used to show state of registers in pipeline
               variable my_line : LINE;   -- not part of working circuit
             begin
               if clk='1' then
                 write(my_line, string'("clock "));
                 write(my_line, counter);
                 write(my_line, string'("  inst="));
                 hwrite(my_line, inst);
                 write(my_line, string'("  PC   ="));
                 hwrite(my_line, PC);
                 write(my_line, string'(" PCnext="));
                 hwrite(my_line, PC_next);
                 writeline(output, my_line);
                 write(my_line, string'("ID  stage  IR="));
                 hwrite(my_line, ID_IR);
                 if (WB_write_enb='1') and (WB_rd/="00000") then
                   write(my_line, string'("  write="));
                   hwrite(my_line, WB_result);
                   write(my_line, string'("  into ="));
                   hwrite(my_line, "000000000000000000000000000"&WB_rd);
                 else
                   write(my_line, string'("                "));
                   write(my_line, string'("                "));
                 end if;
                 write(my_line, string'("                "));
                 write(my_line, string'(" rd="));
                 write(my_line, ID_rd);
                 writeline(output, my_line);

                 write(my_line, string'("EX  stage  IR="));
                 hwrite(my_line, EX_IR);
                 write(my_line, string'("  EX_A ="));
                 hwrite(my_line, EX_A);
                 write(my_line, string'("  EX_B ="));
                 hwrite(my_line, EX_B);
                 write(my_line, string'("  EX_C ="));
                 hwrite(my_line, EX_C);
                 write(my_line, string'(" rd="));
                 write(my_line, EX_rd);
                 writeline(output, my_line);
                 write(my_line, string'("EX  stage"));
                 write(my_line, string'("             "));
                 write(my_line, string'("EX_aluB="));
                 hwrite(my_line, EX_aluB);
                 write(my_line, string'(" EX_res="));
                 hwrite(my_line, EX_result);
                 writeline(output, my_line);

                 write(my_line, string'("MEM stage  IR="));
                 hwrite(my_line, MEM_IR);
                 write(my_line, string'("  addr ="));
                 hwrite(my_line, MEM_addr);
                 write(my_line, string'("  data ="));
                 hwrite(my_line, MEM_data);
                 if MEMread='1' then
                   write(my_line, string'("  read ="));
                   hwrite(my_line, MEM_read_data);
                 elsif MEMWrite='1' then
                   write(my_line, string'("  wrote="));
                   hwrite(my_line, MEM_data);
                 else
                   write(my_line, string'("                "));
                 end if;
                 write(my_line, string'(" rd="));
                 write(my_line, MEM_rd);
                 writeline(output, my_line);
                 write(my_line, string'("WB  stage  IR="));
                 hwrite(my_line, WB_IR);
                 write(my_line, string'("  read ="));
                 hwrite(my_line, WB_read);
                 write(my_line, string'("  pass ="));
                 hwrite(my_line, WB_pass);
                 write(my_line, string'(" result="));
                 hwrite(my_line, WB_result);
                 write(my_line, string'(" rd="));
                 write(my_line, WB_rd);
                 writeline(output, my_line);
                 write(my_line, string'("control RegDst="));
                 write(my_line, RegDst);
                 write(my_line, string'("  ALUSrc="));
                 write(my_line, ALUSrc);
                 write(my_line, string'("  MemtoReg="));
                 write(my_line, MemtoReg);
                 write(my_line, string'("  MEMRead="));
                 write(my_line, MEMRead);
                 write(my_line, string'("  MEMWrite="));
                 write(my_line, MEMWrite);
                 write(my_line, string'("  WB_write_enb="));
                 write(my_line, WB_write_enb);
                 writeline(output, my_line);

                 -- registers
                 write(my_line, string'("reg 0-7 "));
                 hwrite(my_line, reg_mem(0));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(1));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(2));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(3));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(4));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(5));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(6));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(7));
                 writeline(output, my_line);
                 write(my_line, string'("   8-15 "));
                 hwrite(my_line, reg_mem(8));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(9));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(10));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(11));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(12));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(13));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(14));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(15));
                 writeline(output, my_line);
                 write(my_line, string'("  16-23 "));
                 hwrite(my_line, reg_mem(16));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(17));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(18));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(19));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(20));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(21));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(22));
                 write(my_line, string'(" "));
                 hwrite(my_line, reg_mem(23));
                 writeline(output, my_line);
                 
                 -- RAM memory
                 write(my_line, string'("RAM 70- "));
                 hwrite(my_line, memory(28));  -- word at hex 70 byte address
                 write(my_line, string'(" "));
                 hwrite(my_line, memory(29));
                 write(my_line, string'(" "));
                 hwrite(my_line, memory(30));
                 write(my_line, string'(" "));
                 hwrite(my_line, memory(31));
                 write(my_line, string'(" "));
                 hwrite(my_line, memory(32));
                 write(my_line, string'(" "));
                 hwrite(my_line, memory(33));
                 write(my_line, string'(" "));
                 hwrite(my_line, memory(34));
                 write(my_line, string'(" "));
                 hwrite(my_line, memory(35));
                 writeline(output, my_line);

                 writeline(output, my_line);  -- blank line
                 counter <= counter+1;
               end if;
             end process printout;