ncsim: 04.10-p002: (c) Copyright 1995-2002 Cadence Design Systems, Inc. ncsim> run 140 ns clock 0 inst=8C010004 PC =00000000 PCnext=00000004 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 1 inst=8C020008 PC =00000004 PCnext=00000008 ID stage IR=8C010004 rd=00001 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 2 inst=00000000 PC =00000008 PCnext=0000000C ID stage IR=8C020008 rd=00010 EX stage IR=8C010004 EX_A =00000000 EX_B =00000000 EX_C =00000004 rd=00001 EX stage EX_aluB=00000004 EX_res=00000004 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 3 inst=00000000 PC =0000000C PCnext=00000010 ID stage IR=00000000 rd=00000 EX stage IR=8C020008 EX_A =00000000 EX_B =00000000 EX_C =00000008 rd=00010 EX stage EX_aluB=00000008 EX_res=00000008 MEM stage IR=8C010004 addr =00000004 data =00000000 read =22222222 rd=00001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=1 clock 4 inst=00221820 PC =00000010 PCnext=00000014 ID stage IR=00000000 write=22222222 into =00000001 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C020008 addr =00000008 data =00000000 read =33333333 rd=00010 WB stage IR=8C010004 read =22222222 pass =00000004 result=22222222 rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=1 MEMWrite=0 WB_write_enb=1 clock 5 inst=00622022 PC =00000014 PCnext=00000018 ID stage IR=00221820 write=33333333 into =00000002 rd=00010 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=8C020008 read =33333333 pass =00000008 result=33333333 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 6 inst=00012BC1 PC =00000018 PCnext=0000001C ID stage IR=00622022 rd=00010 EX stage IR=00221820 EX_A =22222222 EX_B =33333333 EX_C =00001820 rd=00010 EX stage EX_aluB=00001820 EX_res=22223A42 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 7 inst=00023402 PC =0000001C PCnext=00000020 ID stage IR=00012BC1 rd=00001 EX stage IR=00622022 EX_A =00000000 EX_B =33333333 EX_C =00002022 rd=00010 EX stage EX_aluB=00002022 EX_res=00002022 MEM stage IR=00221820 addr =22223A42 data =33333333 rd=00010 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 8 inst=00033824 PC =00000020 PCnext=00000024 ID stage IR=00023402 write=22223A42 into =00000002 rd=00010 EX stage IR=00012BC1 EX_A =00000000 EX_B =22222222 EX_C =00002BC1 rd=00001 EX stage EX_aluB=00002BC1 EX_res=00002BC1 MEM stage IR=00622022 addr =00002022 data =33333333 rd=00010 WB stage IR=00221820 read =00000000 pass =22223A42 result=22223A42 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 9 inst=AC010008 PC =00000024 PCnext=00000028 ID stage IR=00033824 write=00002022 into =00000002 rd=00011 EX stage IR=00023402 EX_A =00000000 EX_B =22223A42 EX_C =00003402 rd=00010 EX stage EX_aluB=00003402 EX_res=00003402 MEM stage IR=00012BC1 addr =00002BC1 data =22222222 rd=00001 WB stage IR=00622022 read =00000000 pass =00002022 result=00002022 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 10 inst=00000000 PC =00000028 PCnext=0000002C ID stage IR=AC010008 write=00002BC1 into =00000001 rd=00001 EX stage IR=00033824 EX_A =00000000 EX_B =00000000 EX_C =00003824 rd=00011 EX stage EX_aluB=00003824 EX_res=00003824 MEM stage IR=00023402 addr =00003402 data =22223A42 rd=00010 WB stage IR=00012BC1 read =00000000 pass =00002BC1 result=00002BC1 rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 11 inst=00000000 PC =0000002C PCnext=00000030 ID stage IR=00000000 write=00003402 into =00000002 rd=00000 EX stage IR=AC010008 EX_A =00000000 EX_B =00002BC1 EX_C =00000008 rd=00001 EX stage EX_aluB=00000008 EX_res=00000008 MEM stage IR=00033824 addr =00003824 data =00000000 rd=00011 WB stage IR=00023402 read =00000000 pass =00003402 result=00003402 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 12 inst=00000000 PC =00000030 PCnext=00000034 ID stage IR=00000000 write=00003824 into =00000003 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=AC010008 addr =00000008 data =00002BC1 rd=00001 WB stage IR=00033824 read =00000000 pass =00003824 result=00003824 rd=00011 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 clock 13 inst=00000000 PC =00000034 PCnext=00000038 ID stage IR=00000000 write=00000008 into =00000001 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=AC010008 read =00000000 pass =00000008 result=00000008 rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 Ran until 140 NS + 0 ncsim> exit