ncsim: 05.10-s015: (c) Copyright 1995-2004 Cadence Design Systems, Inc. ncsim> run 650 ns ---PC--- --inst-- loadmem process input .abs file 00000000 8C010074 lw $1,w2($0) -- Icache stall 00000004 8C020078 lw $2,w3($0) -- Dcache stall on access w2 00000008 00221820 add $3,$1,$2 -- pipeline stall 0000000C 00222022 sub $4,$1,$2 00000010 00012BC2 sll $5,$1,15 -- Icache stall 00000014 00023403 srl $6,$2,16 00000018 00033805 cmpl $7,$3 0000001C AC01007C sw $1,w4($0) 00000020 1CA80070 addi $8,w1($5) -- Icache stall 00000024 8C0F0070 lw $15,w1($0) 00000028 8C100074 lw $16,w2($0) 0000002C 01F08820 add $17,$15,$16 -- $16 forwarded, stall 00000030 02319020 add $18,$17,$17 -- $17 forwarded on both 00000034 1A320005 beq $17,$18,lab1 -- one stall, no br 00000038 8C090080 lw $9,w5($0) -- always execute 0000003C 8C0C0070 lw $12,w1($0) -- executed 00000040 08000013 j lab1 00000044 8C010078 lw $1,w3($0) -- branch slot, always 00000048 8C0E0070 lw $14,w1($0) -- not executed 0000004C 18410002 lab1: beq $2,$1,lab2 -- forward, does branch 00000050 8C0B0078 lw $11,w3($0) -- always execute 00000054 8C0E0074 lw $14,w2($0) -- not executed 00000058 8C0A0084 lab2: lw $10,w6($0) -- run long enough to load 0000005C 08000017 lab3: j lab3: -- loop until time runs out 00000060 8C0D0080 lw $13,w5($0) -- branch slot, always 00000064 8C0E0078 lw $14,w3($0) -- not executed 00000068 00000000 nop 0000006C 00000000 nop 00000070 11111111 w1: word 0x11111111 00000074 22222222 w2: word 0x22222222 00000078 33333333 w3: word 0x33333333 0000007C 44444444 w4: word 0x44444444 00000080 55555555 w5: word 0x55555555 00000084 66666666 w6: word 0x66666666 loadmem ended. memory loaded clock 0 inst=00000000 PC =00000000 PCnext=00000004 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 1 inst=00000000 PC =00000000 PCnext=00000004 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 2 inst=00000000 PC =00000000 PCnext=00000004 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 3 inst=8C010074 PC =00000000 PCnext=00000004 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 4 inst=8C020078 PC =00000004 PCnext=00000008 ID stage IR=8C010074 rd=00001 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 5 inst=00221820 PC =00000008 PCnext=0000000C ID stage IR=8C020078 rd=00010 EX stage IR=8C010074 EX_A =00000000 EX_B =00000000 EX_C =00000074 rd=00001 EX stage EX_aluB=00000074 EX_res=00000074 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 6 inst=00222022 PC =0000000C PCnext=00000010 ID stage IR=00221820 rd=00000 EX stage IR=8C020078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=00010 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=8C010074 addr =00000074 data =00000000 read =00000000 rd=00001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 7 inst=00222022 PC =0000000C PCnext=00000010 ID stage IR=00221820 rd=00000 EX stage IR=8C020078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=00010 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=8C010074 addr =00000074 data =00000000 read =00000000 rd=00001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 8 inst=00222022 PC =0000000C PCnext=00000010 ID stage IR=00221820 rd=00000 EX stage IR=8C020078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=00010 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=8C010074 addr =00000074 data =00000000 read =00000000 rd=00001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 9 inst=00222022 PC =0000000C PCnext=00000010 ID stage IR=00221820 rd=00000 EX stage IR=8C020078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=00010 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=8C010074 addr =00000074 data =00000000 read =00000000 rd=00001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 10 inst=00222022 PC =0000000C PCnext=00000010 ID stage IR=00221820 rd=00000 EX stage IR=8C020078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=00010 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=8C010074 addr =00000074 data =00000000 read =22222222 rd=00001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 11 inst=00222022 PC =0000000C PCnext=00000010 ID stage IR=00221820 write=22222222 into =00000001 rd=00011 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00001820 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C020078 addr =00000078 data =00000000 read =33333333 rd=00010 WB stage IR=8C010074 read =22222222 pass =00000074 result=22222222 rd=00001 control RegDst=1 ALUSrc=0 MemtoReg=1 MEMRead=1 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 12 inst=00000000 PC =00000010 PCnext=00000014 ID stage IR=00222022 write=33333333 into =00000002 rd=00000 EX stage IR=00221820 EX_A =22222222 EX_B =00000000 EX_C =00001820 rd=00011 EX stage EX_aluB=33333333 EX_res=55555555 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=8C020078 read =33333333 pass =00000078 result=33333333 rd=00010 control RegDst=1 ALUSrc=0 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 13 inst=00000000 PC =00000010 PCnext=00000014 ID stage IR=00222022 rd=00000 EX stage IR=00000000 EX_A =22222222 EX_B =33333333 EX_C =00002022 rd=00000 EX stage EX_aluB=33333333 EX_res=55555555 MEM stage IR=00221820 addr =55555555 data =33333333 rd=00011 WB stage IR=00000000 read =33333333 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 14 inst=00000000 PC =00000010 PCnext=00000014 ID stage IR=00222022 write=55555555 into =00000003 rd=00000 EX stage IR=00000000 EX_A =22222222 EX_B =33333333 EX_C =00002022 rd=00000 EX stage EX_aluB=33333333 EX_res=55555555 MEM stage IR=00000000 addr =55555555 data =33333333 rd=00000 WB stage IR=00221820 read =33333333 pass =55555555 result=55555555 rd=00011 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 15 inst=00012BC2 PC =00000010 PCnext=00000014 ID stage IR=00222022 rd=00100 EX stage IR=00000000 EX_A =22222222 EX_B =33333333 EX_C =00002022 rd=00000 EX stage EX_aluB=33333333 EX_res=55555555 MEM stage IR=00000000 addr =55555555 data =33333333 rd=00000 WB stage IR=00000000 read =33333333 pass =55555555 result=55555555 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 16 inst=00023403 PC =00000014 PCnext=00000018 ID stage IR=00012BC2 rd=00101 EX stage IR=00222022 EX_A =22222222 EX_B =33333333 EX_C =00002022 rd=00100 EX stage EX_aluB=33333333 EX_res=EEEEEEEF MEM stage IR=00000000 addr =55555555 data =33333333 rd=00000 WB stage IR=00000000 read =33333333 pass =55555555 result=55555555 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 17 inst=00033805 PC =00000018 PCnext=0000001C ID stage IR=00023403 rd=00110 EX stage IR=00012BC2 EX_A =00000000 EX_B =22222222 EX_C =00002BC2 rd=00101 EX stage EX_aluB=22222222 EX_res=11110000 MEM stage IR=00222022 addr =EEEEEEEF data =33333333 rd=00100 WB stage IR=00000000 read =33333333 pass =55555555 result=55555555 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 18 inst=AC01007C PC =0000001C PCnext=00000020 ID stage IR=00033805 write=EEEEEEEF into =00000004 rd=00111 EX stage IR=00023403 EX_A =00000000 EX_B =33333333 EX_C =00003403 rd=00110 EX stage EX_aluB=33333333 EX_res=00003333 MEM stage IR=00012BC2 addr =11110000 data =22222222 rd=00101 WB stage IR=00222022 read =33333333 pass =EEEEEEEF result=EEEEEEEF rd=00100 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 19 inst=00000000 PC =00000020 PCnext=00000024 ID stage IR=AC01007C write=11110000 into =00000005 rd=00000 EX stage IR=00033805 EX_A =00000000 EX_B =55555555 EX_C =00003805 rd=00111 EX stage EX_aluB=55555555 EX_res=AAAAAAAA MEM stage IR=00023403 addr =00003333 data =33333333 rd=00110 WB stage IR=00012BC2 read =33333333 pass =11110000 result=11110000 rd=00101 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 20 inst=00000000 PC =00000020 PCnext=00000024 ID stage IR=AC01007C write=00003333 into =00000006 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =22222222 EX_C =0000007C rd=00000 EX stage EX_aluB=22222222 EX_res=22222222 MEM stage IR=00033805 addr =AAAAAAAA data =55555555 rd=00111 WB stage IR=00023403 read =33333333 pass =00003333 result=00003333 rd=00110 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 21 inst=00000000 PC =00000020 PCnext=00000024 ID stage IR=AC01007C write=AAAAAAAA into =00000007 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =22222222 EX_C =0000007C rd=00000 EX stage EX_aluB=22222222 EX_res=22222222 MEM stage IR=00000000 addr =22222222 data =22222222 rd=00000 WB stage IR=00033805 read =33333333 pass =AAAAAAAA result=AAAAAAAA rd=00111 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 22 inst=1CA80070 PC =00000020 PCnext=00000024 ID stage IR=AC01007C rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =22222222 EX_C =0000007C rd=00000 EX stage EX_aluB=22222222 EX_res=22222222 MEM stage IR=00000000 addr =22222222 data =22222222 rd=00000 WB stage IR=00000000 read =33333333 pass =22222222 result=22222222 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 23 inst=8C0F0070 PC =00000024 PCnext=00000028 ID stage IR=1CA80070 rd=01000 EX stage IR=AC01007C EX_A =00000000 EX_B =22222222 EX_C =0000007C rd=00000 EX stage EX_aluB=0000007C EX_res=0000007C MEM stage IR=00000000 addr =22222222 data =22222222 rd=00000 WB stage IR=00000000 read =33333333 pass =22222222 result=22222222 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 55555555 66666666 00000000 00000000 clock 24 inst=8C100074 PC =00000028 PCnext=0000002C ID stage IR=8C0F0070 rd=01111 EX stage IR=1CA80070 EX_A =11110000 EX_B =00000000 EX_C =00000070 rd=01000 EX stage EX_aluB=00000070 EX_res=11110070 MEM stage IR=AC01007C addr =0000007C data =22222222 wrote=22222222 rd=00000 WB stage IR=00000000 read =33333333 pass =22222222 result=22222222 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=1 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 25 inst=01F08820 PC =0000002C PCnext=00000030 ID stage IR=8C100074 rd=10000 EX stage IR=8C0F0070 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=01111 EX stage EX_aluB=00000070 EX_res=00000070 MEM stage IR=1CA80070 addr =11110070 data =00000000 rd=01000 WB stage IR=AC01007C read =22222222 pass =0000007C result=0000007C rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 26 inst=00000000 PC =00000030 PCnext=00000034 ID stage IR=01F08820 write=11110070 into =00000008 rd=00000 EX stage IR=8C100074 EX_A =00000000 EX_B =00000000 EX_C =00000074 rd=10000 EX stage EX_aluB=00000074 EX_res=00000074 MEM stage IR=8C0F0070 addr =00000070 data =00000000 read =11111111 rd=01111 WB stage IR=1CA80070 read =22222222 pass =11110070 result=11110070 rd=01000 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 27 inst=00000000 PC =00000030 PCnext=00000034 ID stage IR=01F08820 write=11111111 into =0000000F rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =FFFF8820 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C100074 addr =00000074 data =00000000 read =22222222 rd=10000 WB stage IR=8C0F0070 read =11111111 pass =00000070 result=11111111 rd=01111 control RegDst=1 ALUSrc=0 MemtoReg=1 MEMRead=1 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 28 inst=00000000 PC =00000030 PCnext=00000034 ID stage IR=01F08820 write=22222222 into =00000010 rd=00000 EX stage IR=00000000 EX_A =11111111 EX_B =00000000 EX_C =FFFF8820 rd=00000 EX stage EX_aluB=00000000 EX_res=11111111 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=8C100074 read =22222222 pass =00000074 result=22222222 rd=10000 control RegDst=1 ALUSrc=0 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 29 inst=02319020 PC =00000030 PCnext=00000034 ID stage IR=01F08820 rd=10001 EX stage IR=00000000 EX_A =11111111 EX_B =22222222 EX_C =FFFF8820 rd=00000 EX stage EX_aluB=22222222 EX_res=33333333 MEM stage IR=00000000 addr =11111111 data =00000000 rd=00000 WB stage IR=00000000 read =22222222 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 30 inst=1A320005 PC =00000034 PCnext=00000038 ID stage IR=02319020 rd=10010 EX stage IR=01F08820 EX_A =11111111 EX_B =22222222 EX_C =FFFF8820 rd=10001 EX stage EX_aluB=22222222 EX_res=33333333 MEM stage IR=00000000 addr =33333333 data =22222222 rd=00000 WB stage IR=00000000 read =22222222 pass =11111111 result=11111111 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 31 inst=8C090080 PC =00000038 PCnext=0000003C ID stage IR=1A320005 rd=00000 EX stage IR=02319020 EX_A =00000000 EX_B =00000000 EX_C =FFFF9020 rd=10010 EX stage EX_aluB=33333333 EX_res=66666666 MEM stage IR=01F08820 addr =33333333 data =22222222 rd=10001 WB stage IR=00000000 read =22222222 pass =33333333 result=33333333 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 32 inst=8C090080 PC =00000038 PCnext=0000003C ID stage IR=1A320005 write=33333333 into =00000011 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000005 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=02319020 addr =66666666 data =33333333 rd=10010 WB stage IR=01F08820 read =22222222 pass =33333333 result=33333333 rd=10001 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 33333333 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 33 inst=8C0C0070 PC =0000003C PCnext=00000040 ID stage IR=8C090080 write=66666666 into =00000012 rd=01001 EX stage IR=1A320005 EX_A =33333333 EX_B =00000000 EX_C =00000005 rd=00000 EX stage EX_aluB=00000005 EX_res=33333338 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=02319020 read =22222222 pass =66666666 result=66666666 rd=10010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 34 inst=00000000 PC =00000040 PCnext=00000044 ID stage IR=8C0C0070 rd=00000 EX stage IR=8C090080 EX_A =00000000 EX_B =00000000 EX_C =00000080 rd=01001 EX stage EX_aluB=00000080 EX_res=00000080 MEM stage IR=1A320005 addr =33333338 data =66666666 rd=00000 WB stage IR=00000000 read =22222222 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 35 inst=00000000 PC =00000040 PCnext=00000044 ID stage IR=8C0C0070 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C090080 addr =00000080 data =00000000 read =22222222 rd=01001 WB stage IR=1A320005 read =22222222 pass =33333338 result=33333338 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 36 inst=00000000 PC =00000040 PCnext=00000044 ID stage IR=8C0C0070 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C090080 addr =00000080 data =00000000 read =22222222 rd=01001 WB stage IR=1A320005 read =22222222 pass =33333338 result=33333338 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 37 inst=08000013 PC =00000040 PCnext=00000044 ID stage IR=8C0C0070 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C090080 addr =00000080 data =00000000 read =22222222 rd=01001 WB stage IR=1A320005 read =22222222 pass =33333338 result=33333338 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 38 inst=08000013 PC =00000040 PCnext=00000044 ID stage IR=8C0C0070 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C090080 addr =00000080 data =00000000 read =22222222 rd=01001 WB stage IR=1A320005 read =22222222 pass =33333338 result=33333338 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 39 inst=08000013 PC =00000040 PCnext=00000044 ID stage IR=8C0C0070 rd=01100 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C090080 addr =00000080 data =00000000 read =55555555 rd=01001 WB stage IR=1A320005 read =22222222 pass =33333338 result=33333338 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 40 inst=8C010078 PC =00000044 PCnext=0000004C ID stage IR=08000013 write=55555555 into =00000009 rd=00000 EX stage IR=8C0C0070 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=01100 EX stage EX_aluB=00000070 EX_res=00000070 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=8C090080 read =55555555 pass =00000080 result=55555555 rd=01001 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 41 inst=18410002 PC =0000004C PCnext=00000050 ID stage IR=8C010078 rd=00001 EX stage IR=08000013 EX_A =00000000 EX_B =00000000 EX_C =00000013 rd=00000 EX stage EX_aluB=00000013 EX_res=00000013 MEM stage IR=8C0C0070 addr =00000070 data =00000000 read =11111111 rd=01100 WB stage IR=00000000 read =55555555 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 42 inst=00000000 PC =00000050 PCnext=00000054 ID stage IR=18410002 write=11111111 into =0000000C rd=00000 EX stage IR=8C010078 EX_A =00000000 EX_B =22222222 EX_C =00000078 rd=00001 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=08000013 addr =00000013 data =00000000 rd=00000 WB stage IR=8C0C0070 read =11111111 pass =00000070 result=11111111 rd=01100 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 00000000 00000000 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 43 inst=00000000 PC =00000050 PCnext=00000054 ID stage IR=18410002 rd=00000 EX stage IR=00000000 EX_A =33333333 EX_B =22222222 EX_C =00000002 rd=00000 EX stage EX_aluB=22222222 EX_res=55555555 MEM stage IR=8C010078 addr =00000078 data =22222222 read =33333333 rd=00001 WB stage IR=08000013 read =11111111 pass =00000013 result=00000013 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 00000000 00000000 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 44 inst=00000000 PC =00000050 PCnext=00000058 ID stage IR=18410002 write=33333333 into =00000001 rd=00000 EX stage IR=00000000 EX_A =33333333 EX_B =22222222 EX_C =00000002 rd=00000 EX stage EX_aluB=22222222 EX_res=55555555 MEM stage IR=00000000 addr =55555555 data =22222222 rd=00000 WB stage IR=8C010078 read =33333333 pass =00000078 result=33333333 rd=00001 control RegDst=0 ALUSrc=0 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 00000000 00000000 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 45 inst=8C0B0078 PC =00000050 PCnext=00000058 ID stage IR=18410002 rd=00000 EX stage IR=00000000 EX_A =33333333 EX_B =33333333 EX_C =00000002 rd=00000 EX stage EX_aluB=33333333 EX_res=66666666 MEM stage IR=00000000 addr =55555555 data =22222222 rd=00000 WB stage IR=00000000 read =33333333 pass =55555555 result=55555555 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 00000000 00000000 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 46 inst=8C0A0084 PC =00000058 PCnext=0000005C ID stage IR=8C0B0078 rd=01011 EX stage IR=18410002 EX_A =33333333 EX_B =33333333 EX_C =00000002 rd=00000 EX stage EX_aluB=00000002 EX_res=33333335 MEM stage IR=00000000 addr =66666666 data =33333333 rd=00000 WB stage IR=00000000 read =33333333 pass =55555555 result=55555555 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 00000000 00000000 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 47 inst=08000017 PC =0000005C PCnext=00000060 ID stage IR=8C0A0084 rd=01010 EX stage IR=8C0B0078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=01011 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=18410002 addr =33333335 data =33333333 rd=00000 WB stage IR=00000000 read =33333333 pass =66666666 result=66666666 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 00000000 00000000 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 48 inst=00000000 PC =00000060 PCnext=0000005C ID stage IR=08000017 rd=00000 EX stage IR=8C0A0084 EX_A =00000000 EX_B =00000000 EX_C =00000084 rd=01010 EX stage EX_aluB=00000084 EX_res=00000084 MEM stage IR=8C0B0078 addr =00000078 data =00000000 read =33333333 rd=01011 WB stage IR=18410002 read =33333333 pass =33333335 result=33333335 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 00000000 00000000 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 49 inst=00000000 PC =00000060 PCnext=0000005C ID stage IR=08000017 write=33333333 into =0000000B rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000017 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C0A0084 addr =00000084 data =00000000 read =66666666 rd=01010 WB stage IR=8C0B0078 read =33333333 pass =00000078 result=33333333 rd=01011 control RegDst=0 ALUSrc=0 MemtoReg=1 MEMRead=1 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 00000000 33333333 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 50 inst=00000000 PC =00000060 PCnext=0000005C ID stage IR=08000017 write=66666666 into =0000000A rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000017 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=8C0A0084 read =66666666 pass =00000084 result=66666666 rd=01010 control RegDst=0 ALUSrc=0 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 51 inst=8C0D0080 PC =00000060 PCnext=0000005C ID stage IR=08000017 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000017 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =66666666 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 52 inst=08000017 PC =0000005C PCnext=00000060 ID stage IR=8C0D0080 rd=01101 EX stage IR=08000017 EX_A =00000000 EX_B =00000000 EX_C =00000017 rd=00000 EX stage EX_aluB=00000017 EX_res=00000017 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =66666666 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 53 inst=8C0D0080 PC =00000060 PCnext=0000005C ID stage IR=08000017 rd=00000 EX stage IR=8C0D0080 EX_A =00000000 EX_B =00000000 EX_C =00000080 rd=01101 EX stage EX_aluB=00000080 EX_res=00000080 MEM stage IR=08000017 addr =00000017 data =00000000 rd=00000 WB stage IR=00000000 read =66666666 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 54 inst=08000017 PC =0000005C PCnext=00000060 ID stage IR=8C0D0080 rd=01101 EX stage IR=08000017 EX_A =00000000 EX_B =00000000 EX_C =00000017 rd=00000 EX stage EX_aluB=00000017 EX_res=00000017 MEM stage IR=8C0D0080 addr =00000080 data =00000000 read =55555555 rd=01101 WB stage IR=08000017 read =66666666 pass =00000017 result=00000017 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 00000000 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 55 inst=8C0D0080 PC =00000060 PCnext=0000005C ID stage IR=08000017 write=55555555 into =0000000D rd=00000 EX stage IR=8C0D0080 EX_A =00000000 EX_B =00000000 EX_C =00000080 rd=01101 EX stage EX_aluB=00000080 EX_res=00000080 MEM stage IR=08000017 addr =00000017 data =00000000 rd=00000 WB stage IR=8C0D0080 read =55555555 pass =00000080 result=55555555 rd=01101 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 55555555 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 56 inst=08000017 PC =0000005C PCnext=00000060 ID stage IR=8C0D0080 rd=01101 EX stage IR=08000017 EX_A =00000000 EX_B =00000000 EX_C =00000017 rd=00000 EX stage EX_aluB=00000017 EX_res=00000017 MEM stage IR=8C0D0080 addr =00000080 data =55555555 read =55555555 rd=01101 WB stage IR=08000017 read =55555555 pass =00000017 result=00000017 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 55555555 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 57 inst=8C0D0080 PC =00000060 PCnext=0000005C ID stage IR=08000017 write=55555555 into =0000000D rd=00000 EX stage IR=8C0D0080 EX_A =00000000 EX_B =55555555 EX_C =00000080 rd=01101 EX stage EX_aluB=00000080 EX_res=00000080 MEM stage IR=08000017 addr =00000017 data =00000000 rd=00000 WB stage IR=8C0D0080 read =55555555 pass =00000080 result=55555555 rd=01101 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 55555555 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 58 inst=08000017 PC =0000005C PCnext=00000060 ID stage IR=8C0D0080 rd=01101 EX stage IR=08000017 EX_A =00000000 EX_B =00000000 EX_C =00000017 rd=00000 EX stage EX_aluB=00000017 EX_res=00000017 MEM stage IR=8C0D0080 addr =00000080 data =55555555 read =55555555 rd=01101 WB stage IR=08000017 read =55555555 pass =00000017 result=00000017 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 55555555 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 59 inst=8C0D0080 PC =00000060 PCnext=0000005C ID stage IR=08000017 write=55555555 into =0000000D rd=00000 EX stage IR=8C0D0080 EX_A =00000000 EX_B =55555555 EX_C =00000080 rd=01101 EX stage EX_aluB=00000080 EX_res=00000080 MEM stage IR=08000017 addr =00000017 data =00000000 rd=00000 WB stage IR=8C0D0080 read =55555555 pass =00000080 result=55555555 rd=01101 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 55555555 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 60 inst=08000017 PC =0000005C PCnext=00000060 ID stage IR=8C0D0080 rd=01101 EX stage IR=08000017 EX_A =00000000 EX_B =00000000 EX_C =00000017 rd=00000 EX stage EX_aluB=00000017 EX_res=00000017 MEM stage IR=8C0D0080 addr =00000080 data =55555555 read =55555555 rd=01101 WB stage IR=08000017 read =55555555 pass =00000017 result=00000017 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 55555555 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 61 inst=8C0D0080 PC =00000060 PCnext=0000005C ID stage IR=08000017 write=55555555 into =0000000D rd=00000 EX stage IR=8C0D0080 EX_A =00000000 EX_B =55555555 EX_C =00000080 rd=01101 EX stage EX_aluB=00000080 EX_res=00000080 MEM stage IR=08000017 addr =00000017 data =00000000 rd=00000 WB stage IR=8C0D0080 read =55555555 pass =00000080 result=55555555 rd=01101 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 55555555 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 62 inst=08000017 PC =0000005C PCnext=00000060 ID stage IR=8C0D0080 rd=01101 EX stage IR=08000017 EX_A =00000000 EX_B =00000000 EX_C =00000017 rd=00000 EX stage EX_aluB=00000017 EX_res=00000017 MEM stage IR=8C0D0080 addr =00000080 data =55555555 read =55555555 rd=01101 WB stage IR=08000017 read =55555555 pass =00000017 result=00000017 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 55555555 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 63 inst=8C0D0080 PC =00000060 PCnext=0000005C ID stage IR=08000017 write=55555555 into =0000000D rd=00000 EX stage IR=8C0D0080 EX_A =00000000 EX_B =55555555 EX_C =00000080 rd=01101 EX stage EX_aluB=00000080 EX_res=00000080 MEM stage IR=08000017 addr =00000017 data =00000000 rd=00000 WB stage IR=8C0D0080 read =55555555 pass =00000080 result=55555555 rd=01101 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 55555555 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 clock 64 inst=08000017 PC =0000005C PCnext=00000060 ID stage IR=8C0D0080 rd=01101 EX stage IR=08000017 EX_A =00000000 EX_B =00000000 EX_C =00000017 rd=00000 EX stage EX_aluB=00000017 EX_res=00000017 MEM stage IR=8C0D0080 addr =00000080 data =55555555 read =55555555 rd=01101 WB stage IR=08000017 read =55555555 pass =00000017 result=00000017 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 33333333 33333333 55555555 EEEEEEEF 11110000 00003333 AAAAAAAA 8-15 11110070 55555555 66666666 33333333 11111111 55555555 00000000 11111111 16-23 22222222 33333333 66666666 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 22222222 55555555 66666666 00000000 00000000 Ran until 650 NS + 0 ncsim> exit