Symphony EDA (R) VHDL Compiler/Simulator Module VhdlE, Version 2.2, Build#6. Copyright(C) Symphony EDA 1997-2003. All rights reserved. Maximum Simulation Time: 250 ns Reading C:\Program Files\Symphony EDA\VHDL Simili 2.2\bin\symphony.ini ... Library 'ieee' ==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly) Library 'work' ==> work.sym Reading work.sym\part2a\prim.var Reading work.sym\part2a\_schematic.var Reading $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_1164\_body.var Reading $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_textio\_body.var Reading work.sym\util_pkg\_body.var Reading work.sym\register_32\prim.var Reading work.sym\add32\prim.var Reading work.sym\instruction_memory\prim.var Reading work.sym\mux32_3\prim.var Reading work.sym\mux_32\prim.var Reading work.sym\registers\prim.var Reading work.sym\mux_5\prim.var Reading work.sym\register_5\prim.var Reading work.sym\alu_32\prim.var Reading work.sym\data_memory\prim.var Reading work.sym\register_32\_behavior.var Reading work.sym\add32\_circuits.var Reading work.sym\add4\prim.var Reading work.sym\add4\_circuits.var Reading work.sym\fadd\prim.var Reading work.sym\fadd\_circuits.var Reading work.sym\instruction_memory\_behavior.var Reading work.sym\mux32_3\_behavior.var Reading work.sym\mux_32\_behavior.var Reading work.sym\registers\_behavior.var Reading work.sym\mux_5\_behavior.var Reading work.sym\register_5\_behavior.var Reading work.sym\alu_32\_schematic.var Reading work.sym\bshift\prim.var Reading work.sym\bshift\_circuits.var Reading work.sym\data_memory\_behavior.var Warning: ****Reducing simulation speed to super slow mode! # of Signals = 7911 # of Components = 172 # of Processes = 315 # of Drivers = 2314 Design Load/Elaboration Elapsed Time: 00h:00m:00s:451ms ---PC--- --inst-- loadmem process reading .abs file 00000000 8C0F0074 lw $15,w1($0) 00000004 8C100078 lw $16,w2($0) 00000008 00000000 nop -- must wait to do add 0000000C 01F08824 and $17,$15,$16 -- $16 forwarded 00000010 02319020 add $18,$17,$17 -- $17 forwarded on both 00000014 00000000 nop -- must wait to do beq 00000018 26320005 beq $17,$18,lab1 -- $18 forwarded, no br 0000001C 8C010074 lw $1,w1($0) 00000020 0800000C j lab1 00000024 8C020074 lw $2,w1($0) -- branch slot, always 00000028 8C0A0088 lw $10,w6($0) -- not executed 0000002C 00000000 nop 00000030 AC010078 lab1: sw $1,w2($0) 00000034 AC020080 sw $2,w4($0) 00000038 24410003 beq $2,$1,lab2 -- no forward, does branch 0000003C 8C080078 lw $8,w2($0) -- always execute 00000040 8C090088 lw $9,w6($0) -- not executed 00000044 00000000 nop 00000048 8C050084 lab2: lw $5,w5($0) 0000004C 24500002 beq $2,$16,lab4 -- no forward, no branch 00000050 8C060088 lw $6,w6($0) 00000054 1C070074 addi $7,w1($0) 00000058 ACE60000 lab4: sw $6,0($7) 0000005C AC070084 sw $7,w5($0) 00000060 00000000 nop 00000064 00000000 nop 00000068 00000000 nop 0000006C 00000000 nop 00000070 00000000 nop 00000074 11111111 w1: word 0x11111111 00000078 22222222 w2: word 0x22222222 0000007C 33333333 w3: word 0x33333333 00000080 44444444 w4: word 0x44444444 00000084 55555555 w5: word 0x55555555 00000088 66666666 w6: word 0x66666666 loadmem complete. memory loaded clock 0 inst=8C0F0074 PC =00000000 PCnext=00000004 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 1 inst=8C100078 PC =00000004 PCnext=00000008 ID stage IR=8C0F0074 rd=01111 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 2 inst=00000000 PC =00000008 PCnext=0000000C ID stage IR=8C100078 rd=10000 EX stage IR=8C0F0074 EX_A =00000000 EX_B =00000000 EX_C =00000074 rd=01111 EX stage EX_aluB=00000074 EX_res=00000074 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 3 inst=01F08824 PC =0000000C PCnext=00000010 ID stage IR=00000000 rd=00000 EX stage IR=8C100078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=10000 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=8C0F0074 addr =00000074 data =00000000 read =11111111 rd=01111 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 4 inst=02319020 PC =00000010 PCnext=00000014 ID stage IR=01F08824 write=11111111 into =0000000F rd=10001 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C100078 addr =00000078 data =00000000 read =22222222 rd=10000 WB stage IR=8C0F0074 read =11111111 pass =00000074 result=11111111 rd=01111 control RegDst=1 ALUSrc=0 MemtoReg=1 MEMRead=1 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 5 inst=00000000 PC =00000014 PCnext=00000018 ID stage IR=02319020 write=22222222 into =00000010 rd=10010 EX stage IR=01F08824 EX_A =11111111 EX_B =00000000 EX_C =FFFF8824 rd=10001 EX stage EX_aluB=22222222 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=8C100078 read =22222222 pass =00000078 result=22222222 rd=10000 control RegDst=1 ALUSrc=0 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 6 inst=26320005 PC =00000018 PCnext=0000001C ID stage IR=00000000 rd=00000 EX stage IR=02319020 EX_A =00000000 EX_B =00000000 EX_C =FFFF9020 rd=10010 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=01F08824 addr =00000000 data =22222222 rd=10001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 7 inst=8C010074 PC =0000001C PCnext=00000030 ID stage IR=26320005 write=00000000 into =00000011 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=02319020 addr =00000000 data =00000000 rd=10010 WB stage IR=01F08824 read =00000000 pass =00000000 result=00000000 rd=10001 control RegDst=0 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 8 inst=AC010078 PC =00000030 PCnext=00000034 ID stage IR=8C010074 write=00000000 into =00000012 rd=00001 EX stage IR=26320005 EX_A =00000000 EX_B =00000000 EX_C =00000005 rd=00000 EX stage EX_aluB=00000005 EX_res=00000005 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=02319020 read =00000000 pass =00000000 result=00000000 rd=10010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 9 inst=AC020080 PC =00000034 PCnext=00000038 ID stage IR=AC010078 rd=00000 EX stage IR=8C010074 EX_A =00000000 EX_B =00000000 EX_C =00000074 rd=00001 EX stage EX_aluB=00000074 EX_res=00000074 MEM stage IR=26320005 addr =00000005 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 10 inst=24410003 PC =00000038 PCnext=0000003C ID stage IR=AC020080 rd=00000 EX stage IR=AC010078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=00000 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=8C010074 addr =00000074 data =00000000 read =11111111 rd=00001 WB stage IR=26320005 read =00000000 pass =00000005 result=00000005 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 22222222 33333333 44444444 55555555 66666666 00000000 clock 11 inst=8C080078 PC =0000003C PCnext=00000040 ID stage IR=24410003 write=11111111 into =00000001 rd=00000 EX stage IR=AC020080 EX_A =00000000 EX_B =00000000 EX_C =00000080 rd=00000 EX stage EX_aluB=00000080 EX_res=00000080 MEM stage IR=AC010078 addr =00000078 data =00000000 wrote=00000000 rd=00000 WB stage IR=8C010074 read =11111111 pass =00000074 result=11111111 rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=1 WB_write_enb=1 reg 0-7 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 00000000 33333333 44444444 55555555 66666666 00000000 clock 12 inst=8C090088 PC =00000040 PCnext=00000044 ID stage IR=8C080078 rd=01000 EX stage IR=24410003 EX_A =00000000 EX_B =11111111 EX_C =00000003 rd=00000 EX stage EX_aluB=00000003 EX_res=00000003 MEM stage IR=AC020080 addr =00000080 data =00000000 wrote=00000000 rd=00000 WB stage IR=AC010078 read =00000000 pass =00000078 result=00000078 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=1 WB_write_enb=0 reg 0-7 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 00000000 33333333 00000000 55555555 66666666 00000000 clock 13 inst=00000000 PC =00000044 PCnext=00000048 ID stage IR=8C090088 rd=01001 EX stage IR=8C080078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=01000 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=24410003 addr =00000003 data =11111111 rd=00000 WB stage IR=AC020080 read =00000000 pass =00000080 result=00000080 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 00000000 33333333 00000000 55555555 66666666 00000000 clock 14 inst=8C050084 PC =00000048 PCnext=0000004C ID stage IR=00000000 rd=00000 EX stage IR=8C090088 EX_A =00000000 EX_B =00000000 EX_C =00000088 rd=01001 EX stage EX_aluB=00000088 EX_res=00000088 MEM stage IR=8C080078 addr =00000078 data =00000000 read =00000000 rd=01000 WB stage IR=24410003 read =00000000 pass =00000003 result=00000003 rd=00000 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 00000000 33333333 00000000 55555555 66666666 00000000 clock 15 inst=24500002 PC =0000004C PCnext=00000050 ID stage IR=8C050084 write=00000000 into =00000008 rd=00101 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C090088 addr =00000088 data =00000000 read =66666666 rd=01001 WB stage IR=8C080078 read =00000000 pass =00000078 result=00000000 rd=01000 control RegDst=0 ALUSrc=0 MemtoReg=1 MEMRead=1 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 00000000 33333333 00000000 55555555 66666666 00000000 clock 16 inst=8C060088 PC =00000050 PCnext=00000054 ID stage IR=24500002 write=66666666 into =00000009 rd=00000 EX stage IR=8C050084 EX_A =00000000 EX_B =00000000 EX_C =00000084 rd=00101 EX stage EX_aluB=00000084 EX_res=00000084 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=8C090088 read =66666666 pass =00000088 result=66666666 rd=01001 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 66666666 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 00000000 33333333 00000000 55555555 66666666 00000000 clock 17 inst=1C070074 PC =00000054 PCnext=00000058 ID stage IR=8C060088 rd=00110 EX stage IR=24500002 EX_A =00000000 EX_B =22222222 EX_C =00000002 rd=00000 EX stage EX_aluB=00000002 EX_res=00000002 MEM stage IR=8C050084 addr =00000084 data =00000000 read =55555555 rd=00101 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 66666666 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 00000000 33333333 00000000 55555555 66666666 00000000 clock 18 inst=ACE60000 PC =00000058 PCnext=0000005C ID stage IR=1C070074 write=55555555 into =00000005 rd=00111 EX stage IR=8C060088 EX_A =00000000 EX_B =00000000 EX_C =00000088 rd=00110 EX stage EX_aluB=00000088 EX_res=00000088 MEM stage IR=24500002 addr =00000002 data =22222222 rd=00000 WB stage IR=8C050084 read =55555555 pass =00000084 result=55555555 rd=00101 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 11111111 00000000 00000000 00000000 55555555 00000000 00000000 8-15 00000000 66666666 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 00000000 33333333 00000000 55555555 66666666 00000000 clock 19 inst=AC070084 PC =0000005C PCnext=00000060 ID stage IR=ACE60000 rd=00000 EX stage IR=1C070074 EX_A =00000000 EX_B =00000000 EX_C =00000074 rd=00111 EX stage EX_aluB=00000074 EX_res=00000074 MEM stage IR=8C060088 addr =00000088 data =00000000 read =66666666 rd=00110 WB stage IR=24500002 read =00000000 pass =00000002 result=00000002 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 00000000 00000000 00000000 55555555 00000000 00000000 8-15 00000000 66666666 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 00000000 33333333 00000000 55555555 66666666 00000000 clock 20 inst=00000000 PC =00000060 PCnext=00000064 ID stage IR=AC070084 write=66666666 into =00000006 rd=00000 EX stage IR=ACE60000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000074 MEM stage IR=1C070074 addr =00000074 data =00000000 rd=00111 WB stage IR=8C060088 read =66666666 pass =00000088 result=66666666 rd=00110 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 11111111 00000000 00000000 00000000 55555555 66666666 00000000 8-15 00000000 66666666 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 11111111 00000000 33333333 00000000 55555555 66666666 00000000 clock 21 inst=00000000 PC =00000064 PCnext=00000068 ID stage IR=00000000 write=00000074 into =00000007 rd=00000 EX stage IR=AC070084 EX_A =00000000 EX_B =00000000 EX_C =00000084 rd=00000 EX stage EX_aluB=00000084 EX_res=00000084 MEM stage IR=ACE60000 addr =00000074 data =66666666 wrote=66666666 rd=00000 WB stage IR=1C070074 read =00000000 pass =00000074 result=00000074 rd=00111 control RegDst=1 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=1 WB_write_enb=1 reg 0-7 00000000 11111111 00000000 00000000 00000000 55555555 66666666 00000074 8-15 00000000 66666666 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 66666666 00000000 33333333 00000000 55555555 66666666 00000000 clock 22 inst=00000000 PC =00000068 PCnext=0000006C ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=AC070084 addr =00000084 data =00000074 wrote=00000074 rd=00000 WB stage IR=ACE60000 read =66666666 pass =00000074 result=00000074 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=1 WB_write_enb=0 reg 0-7 00000000 11111111 00000000 00000000 00000000 55555555 66666666 00000074 8-15 00000000 66666666 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 66666666 00000000 33333333 00000000 00000074 66666666 00000000 clock 23 inst=00000000 PC =0000006C PCnext=00000070 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=AC070084 read =00000074 pass =00000084 result=00000084 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 00000000 00000000 00000000 55555555 66666666 00000074 8-15 00000000 66666666 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 66666666 00000000 33333333 00000000 00000074 66666666 00000000 clock 24 inst=00000000 PC =00000070 PCnext=00000074 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=1 ALUSrc=0 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 11111111 00000000 00000000 00000000 55555555 66666666 00000074 8-15 00000000 66666666 00000000 00000000 00000000 00000000 00000000 11111111 16-23 22222222 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 00000000 66666666 00000000 33333333 00000000 00000074 66666666 00000000 Simulation stopped at: 250 ns Simulation Elapsed Time: 00h:00m:51s:995ms Total Kernel Time: 00h:00m:00s:290ms Total User Time: 00h:00m:26s:608ms