ncsim: v03.11.(s015): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc. ncsim> run 230 ns loadmem process reading file 00000000000000000000000000000000 =loc 10001100000000010000000001100100 =val 00000000000000000000000000000100 =loc 10001100000000100000000001101000 =val 00000000000000000000000000001000 =loc 00000000000000000000000000000000 =val 00000000000000000000000000001100 =loc 00000000000000000000000000000000 =val 00000000000000000000000000010000 =loc 00000000001000100001100000100000 =val 00000000000000000000000000010100 =loc 00000000001000100010000000100010 =val 00000000000000000000000000011000 =loc 00000000000000010010101111000001 =val 00000000000000000000000000011100 =loc 00000000000000100011010000000010 =val 00000000000000000000000000100000 =loc 00000000000000110011100000000100 =val 00000000000000000000000000100100 =loc 10101100000000010000000001101100 =val 00000000000000000000000000101000 =loc 00100000000010000000000001100000 =val 00000000000000000000000000101100 =loc 00000000000000000000000000000000 =val 00000000000000000000000000110000 =loc 00000000000000000000000000000000 =val 00000000000000000000000000110100 =loc 10001101000010010000000000000100 =val 00000000000000000000000000111000 =loc 00100001000010100000000000001000 =val 00000000000000000000000000111100 =loc 00000000000000000000000000000000 =val 00000000000000000000000001000000 =loc 00000000000000000000000000000000 =val 00000000000000000000000001000100 =loc 10101101010000110000000000000000 =val 00000000000000000000000001001000 =loc 00000000000000000000000000000000 =val 00000000000000000000000001001100 =loc 00000000000000000000000000000000 =val 00000000000000000000000001010000 =loc 00000000000000000000000000000000 =val 00000000000000000000000001010100 =loc 00000000000000000000000000000000 =val 00000000000000000000000001011000 =loc 00000000000000000000000000000000 =val 00000000000000000000000001011100 =loc 00000000000000000000000000000000 =val 00000000000000000000000001100000 =loc 00010001000100010001000100010001 =val 00000000000000000000000001100100 =loc 00100010001000100010001000100010 =val 00000000000000000000000001101000 =loc 00110011001100110011001100110011 =val 00000000000000000000000001101100 =loc 01000100010001000100010001000100 =val loadmem done. memory loaded clock 0 inst=8C010064 PC =00000000 PCnext=00000004 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 1 inst=8C020068 PC =00000004 PCnext=00000008 ID stage IR=8C010064 rd=00001 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 2 inst=00000000 PC =00000008 PCnext=0000000C ID stage IR=8C020068 rd=00010 EX stage IR=8C010064 EX_A =00000000 EX_B =00000000 EX_C =00000064 rd=00001 EX stage EX_aluB=00000064 EX_res=00000064 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 3 inst=00000000 PC =0000000C PCnext=00000010 ID stage IR=00000000 rd=00000 EX stage IR=8C020068 EX_A =00000000 EX_B =00000000 EX_C =00000068 rd=00010 EX stage EX_aluB=00000068 EX_res=00000068 MEM stage IR=8C010064 addr =00000064 data =00000000 read =22222222 rd=00001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 4 inst=00221820 PC =00000010 PCnext=00000014 ID stage IR=00000000 write=22222222 into =00000001 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C020068 addr =00000068 data =00000000 read =33333333 rd=00010 WB stage IR=8C010064 read =22222222 pass =00000064 result=22222222 rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=1 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 5 inst=00222022 PC =00000014 PCnext=00000018 ID stage IR=00221820 write=33333333 into =00000002 rd=00010 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=8C020068 read =33333333 pass =00000068 result=33333333 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 6 inst=00012BC1 PC =00000018 PCnext=0000001C ID stage IR=00222022 rd=00010 EX stage IR=00221820 EX_A =22222222 EX_B =33333333 EX_C =00001820 rd=00010 EX stage EX_aluB=00001820 EX_res=22223A42 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 7 inst=00023402 PC =0000001C PCnext=00000020 ID stage IR=00012BC1 rd=00001 EX stage IR=00222022 EX_A =22222222 EX_B =33333333 EX_C =00002022 rd=00010 EX stage EX_aluB=00002022 EX_res=22224244 MEM stage IR=00221820 addr =22223A42 data =33333333 rd=00010 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 8 inst=00033804 PC =00000020 PCnext=00000024 ID stage IR=00023402 rd=00010 EX stage IR=00012BC1 EX_A =00000000 EX_B =22222222 EX_C =00002BC1 rd=00001 EX stage EX_aluB=00002BC1 EX_res=00002BC1 MEM stage IR=00222022 addr =22224244 data =33333333 rd=00010 WB stage IR=00221820 read =00000000 pass =22223A42 result=22223A42 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 9 inst=AC01006C PC =00000024 PCnext=00000028 ID stage IR=00033804 rd=00011 EX stage IR=00023402 EX_A =00000000 EX_B =33333333 EX_C =00003402 rd=00010 EX stage EX_aluB=00003402 EX_res=00003402 MEM stage IR=00012BC1 addr =00002BC1 data =22222222 rd=00001 WB stage IR=00222022 read =00000000 pass =22224244 result=22224244 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 10 inst=20080060 PC =00000028 PCnext=0000002C ID stage IR=AC01006C rd=00001 EX stage IR=00033804 EX_A =00000000 EX_B =00000000 EX_C =00003804 rd=00011 EX stage EX_aluB=00003804 EX_res=00003804 MEM stage IR=00023402 addr =00003402 data =33333333 rd=00010 WB stage IR=00012BC1 read =00000000 pass =00002BC1 result=00002BC1 rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 11 inst=00000000 PC =0000002C PCnext=00000030 ID stage IR=20080060 rd=01000 EX stage IR=AC01006C EX_A =00000000 EX_B =22222222 EX_C =0000006C rd=00001 EX stage EX_aluB=0000006C EX_res=0000006C MEM stage IR=00033804 addr =00003804 data =00000000 rd=00011 WB stage IR=00023402 read =00000000 pass =00003402 result=00003402 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 12 inst=00000000 PC =00000030 PCnext=00000034 ID stage IR=00000000 rd=00000 EX stage IR=20080060 EX_A =00000000 EX_B =00000000 EX_C =00000060 rd=01000 EX stage EX_aluB=00000060 EX_res=00000060 MEM stage IR=AC01006C addr =0000006C data =22222222 rd=00001 WB stage IR=00033804 read =00000000 pass =00003804 result=00003804 rd=00011 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 13 inst=8D090004 PC =00000034 PCnext=00000038 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=20080060 addr =00000060 data =00000000 rd=01000 WB stage IR=AC01006C read =00000000 pass =0000006C result=0000006C rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 14 inst=210A0008 PC =00000038 PCnext=0000003C ID stage IR=8D090004 rd=01001 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=20080060 read =00000000 pass =00000060 result=00000060 rd=01000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 15 inst=00000000 PC =0000003C PCnext=00000040 ID stage IR=210A0008 rd=01010 EX stage IR=8D090004 EX_A =00000000 EX_B =00000000 EX_C =00000004 rd=01001 EX stage EX_aluB=00000004 EX_res=00000004 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 16 inst=00000000 PC =00000040 PCnext=00000044 ID stage IR=00000000 rd=00000 EX stage IR=210A0008 EX_A =00000000 EX_B =00000000 EX_C =00000008 rd=01010 EX stage EX_aluB=00000008 EX_res=00000008 MEM stage IR=8D090004 addr =00000004 data =00000000 read =8C020068 rd=01001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 17 inst=AD430000 PC =00000044 PCnext=00000048 ID stage IR=00000000 write=8C020068 into =00000009 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=210A0008 addr =00000008 data =00000000 rd=01010 WB stage IR=8D090004 read =8C020068 pass =00000004 result=8C020068 rd=01001 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020068 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 18 inst=00000000 PC =00000048 PCnext=0000004C ID stage IR=AD430000 rd=00011 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=210A0008 read =00000000 pass =00000008 result=00000008 rd=01010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020068 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 19 inst=00000000 PC =0000004C PCnext=00000050 ID stage IR=00000000 rd=00000 EX stage IR=AD430000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00011 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020068 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 20 inst=00000000 PC =00000050 PCnext=00000054 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=AD430000 addr =00000000 data =00000000 rd=00011 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020068 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 21 inst=00000000 PC =00000054 PCnext=00000058 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=AD430000 read =00000000 pass =00000000 result=00000000 rd=00011 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020068 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 22 inst=00000000 PC =00000058 PCnext=0000005C ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020068 00000000 00000000 00000000 00000000 00000000 00000000 RAM 60- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 Ran until 230 NS + 0 ncsim> exit