ncsim: 06.11-s008: (c) Copyright 1995-2007 Cadence Design Systems, Inc. ncsim> run 230 ns ---PC--- --inst-- loadmem process input .abs file 00000000 8C010074 lw $1,w2($0) 00000004 8C020078 lw $2,w3($0) 00000008 00000000 nop 0000000C 00000000 nop 00000010 00221820 add $3,$1,$2 00000014 00222022 sub $4,$1,$2 00000018 00012BC2 sll $5,$1,15 0000001C 00023404 srl $6,$2,16 00000020 0003380F cmpl $7,$3 00000024 0022580A and $11,$1,$2 00000028 AC01007C sw $1,w4($0) 0000002C 3C080070 addi $8,w1 00000030 00000000 nop 00000034 00000000 nop 00000038 8D090004 lw $9,4($8) 0000003C 3D0A0008 addi $10,8($8) 00000040 00000000 nop 00000044 00000000 nop 00000048 AD430000 sw $3,0($10) 0000004C 00000000 nop 00000050 00000000 nop 00000054 00000000 nop 00000058 00000000 nop 0000005C 00000000 nop 00000060 00000000 nop 00000064 00000000 nop 00000068 00000000 nop 0000006C 00000000 nop 00000070 11111111 w1: word 0x11111111 00000074 22222222 w2: word 0x22222222 00000078 33333333 w3: word 0x33333333 0000007C 44444444 w4: word 0x44444444 loadmem finished. memory loaded clock 0 inst=8C010074 PC =00000000 PCnext=00000004 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 1 inst=8C020078 PC =00000004 PCnext=00000008 ID stage IR=8C010074 rd=00001 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 2 inst=00000000 PC =00000008 PCnext=0000000C ID stage IR=8C020078 rd=00010 EX stage IR=8C010074 EX_A =00000000 EX_B =00000000 EX_C =00000074 rd=00001 EX stage EX_aluB=00000074 EX_res=00000074 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 3 inst=00000000 PC =0000000C PCnext=00000010 ID stage IR=00000000 rd=00000 EX stage IR=8C020078 EX_A =00000000 EX_B =00000000 EX_C =00000078 rd=00010 EX stage EX_aluB=00000078 EX_res=00000078 MEM stage IR=8C010074 addr =00000074 data =00000000 read =22222222 rd=00001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 4 inst=00221820 PC =00000010 PCnext=00000014 ID stage IR=00000000 write=22222222 into =00000001 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=8C020078 addr =00000078 data =00000000 read =33333333 rd=00010 WB stage IR=8C010074 read =22222222 pass =00000074 result=22222222 rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=1 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 00000000 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 5 inst=00222022 PC =00000014 PCnext=00000018 ID stage IR=00221820 write=33333333 into =00000002 rd=00010 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=8C020078 read =33333333 pass =00000078 result=33333333 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 6 inst=00012BC2 PC =00000018 PCnext=0000001C ID stage IR=00222022 rd=00010 EX stage IR=00221820 EX_A =22222222 EX_B =33333333 EX_C =00001820 rd=00010 EX stage EX_aluB=00001820 EX_res=22223A42 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 7 inst=00023404 PC =0000001C PCnext=00000020 ID stage IR=00012BC2 rd=00001 EX stage IR=00222022 EX_A =22222222 EX_B =33333333 EX_C =00002022 rd=00010 EX stage EX_aluB=00002022 EX_res=22224244 MEM stage IR=00221820 addr =22223A42 data =33333333 rd=00010 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 8 inst=0003380F PC =00000020 PCnext=00000024 ID stage IR=00023404 rd=00010 EX stage IR=00012BC2 EX_A =00000000 EX_B =22222222 EX_C =00002BC2 rd=00001 EX stage EX_aluB=00002BC2 EX_res=00002BC2 MEM stage IR=00222022 addr =22224244 data =33333333 rd=00010 WB stage IR=00221820 read =00000000 pass =22223A42 result=22223A42 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 9 inst=0022580A PC =00000024 PCnext=00000028 ID stage IR=0003380F rd=00011 EX stage IR=00023404 EX_A =00000000 EX_B =33333333 EX_C =00003404 rd=00010 EX stage EX_aluB=00003404 EX_res=00003404 MEM stage IR=00012BC2 addr =00002BC2 data =22222222 rd=00001 WB stage IR=00222022 read =00000000 pass =22224244 result=22224244 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 10 inst=AC01007C PC =00000028 PCnext=0000002C ID stage IR=0022580A rd=00010 EX stage IR=0003380F EX_A =00000000 EX_B =00000000 EX_C =0000380F rd=00011 EX stage EX_aluB=0000380F EX_res=0000380F MEM stage IR=00023404 addr =00003404 data =33333333 rd=00010 WB stage IR=00012BC2 read =00000000 pass =00002BC2 result=00002BC2 rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 11 inst=3C080070 PC =0000002C PCnext=00000030 ID stage IR=AC01007C rd=00001 EX stage IR=0022580A EX_A =22222222 EX_B =33333333 EX_C =0000580A rd=00010 EX stage EX_aluB=0000580A EX_res=22227A2C MEM stage IR=0003380F addr =0000380F data =00000000 rd=00011 WB stage IR=00023404 read =00000000 pass =00003404 result=00003404 rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 12 inst=00000000 PC =00000030 PCnext=00000034 ID stage IR=3C080070 rd=01000 EX stage IR=AC01007C EX_A =00000000 EX_B =22222222 EX_C =0000007C rd=00001 EX stage EX_aluB=0000007C EX_res=0000007C MEM stage IR=0022580A addr =22227A2C data =33333333 rd=00010 WB stage IR=0003380F read =00000000 pass =0000380F result=0000380F rd=00011 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 13 inst=00000000 PC =00000034 PCnext=00000038 ID stage IR=00000000 rd=00000 EX stage IR=3C080070 EX_A =00000000 EX_B =00000000 EX_C =00000070 rd=01000 EX stage EX_aluB=00000070 EX_res=00000070 MEM stage IR=AC01007C addr =0000007C data =22222222 rd=00001 WB stage IR=0022580A read =00000000 pass =22227A2C result=22227A2C rd=00010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 14 inst=8D090004 PC =00000038 PCnext=0000003C ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=3C080070 addr =00000070 data =00000000 rd=01000 WB stage IR=AC01007C read =00000000 pass =0000007C result=0000007C rd=00001 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 15 inst=3D0A0008 PC =0000003C PCnext=00000040 ID stage IR=8D090004 rd=01001 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=3C080070 read =00000000 pass =00000070 result=00000070 rd=01000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 16 inst=00000000 PC =00000040 PCnext=00000044 ID stage IR=3D0A0008 rd=01010 EX stage IR=8D090004 EX_A =00000000 EX_B =00000000 EX_C =00000004 rd=01001 EX stage EX_aluB=00000004 EX_res=00000004 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 17 inst=00000000 PC =00000044 PCnext=00000048 ID stage IR=00000000 rd=00000 EX stage IR=3D0A0008 EX_A =00000000 EX_B =00000000 EX_C =00000008 rd=01010 EX stage EX_aluB=00000008 EX_res=00000008 MEM stage IR=8D090004 addr =00000004 data =00000000 read =8C020078 rd=01001 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=1 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 18 inst=AD430000 PC =00000048 PCnext=0000004C ID stage IR=00000000 write=8C020078 into =00000009 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=3D0A0008 addr =00000008 data =00000000 rd=01010 WB stage IR=8D090004 read =8C020078 pass =00000004 result=8C020078 rd=01001 control RegDst=0 ALUSrc=1 MemtoReg=1 MEMRead=0 MEMWrite=0 WB_write_enb=1 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020078 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 19 inst=00000000 PC =0000004C PCnext=00000050 ID stage IR=AD430000 rd=00011 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=3D0A0008 read =00000000 pass =00000008 result=00000008 rd=01010 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020078 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 20 inst=00000000 PC =00000050 PCnext=00000054 ID stage IR=00000000 rd=00000 EX stage IR=AD430000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00011 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020078 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 21 inst=00000000 PC =00000054 PCnext=00000058 ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=AD430000 addr =00000000 data =00000000 rd=00011 WB stage IR=00000000 read =00000000 pass =00000000 result=00000000 rd=00000 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020078 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 clock 22 inst=00000000 PC =00000058 PCnext=0000005C ID stage IR=00000000 rd=00000 EX stage IR=00000000 EX_A =00000000 EX_B =00000000 EX_C =00000000 rd=00000 EX stage EX_aluB=00000000 EX_res=00000000 MEM stage IR=00000000 addr =00000000 data =00000000 rd=00000 WB stage IR=AD430000 read =00000000 pass =00000000 result=00000000 rd=00011 control RegDst=0 ALUSrc=1 MemtoReg=0 MEMRead=0 MEMWrite=0 WB_write_enb=0 reg 0-7 00000000 22222222 33333333 00000000 00000000 00000000 00000000 00000000 8-15 00000000 8C020078 00000000 00000000 00000000 00000000 00000000 00000000 16-23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RAM 70- 11111111 22222222 33333333 44444444 00000000 00000000 00000000 00000000 Ran until 230 NS + 0 ncsim> exit