// div_ser4  division implemented as serial adds (one 4 bit adder)
//          needs components  add4c  from add4c.e
// Book, p333, problem 4.54

define cntr2(clk, cntr[2]) // 2 bit counter and clock generator
circuits
  clk     <= ~clk after 30ns;
  cntr[0] <= ~cntr[0] on falling clk     after 1ns;
  cntr[1] <= ~cntr[1] on falling cntr[0] after 1ns;
end circuits;
end cntr2;

  //             7 / 2 = 3 with remainder 1 
signal md[4] <= #h2; // divisor
signal hi[4] <= #h0; // top of dividend (will end up remainder)
signal lo[4] <= #h7; // bottom of dividend (will end up quotient)
signal sum[4];
signal cout;
signal a[4]; // shifted dividend
signal b[4]; // md if sub_add==0  else  ~md if sub_add==1
signal quo <= #b0;
signal sub_add <= #b1; // first operation is always subtract (also cin)
signal clk <= #b1;
signal cntr[2] <= #b00;
signal enb <= #b1;
signal divclk <= #b1;  // only run four steps for four bit divide

circuits 
  counter use cntr2(clk, cntr);
  enb <= #b0 when (cntr==#b11) else enb on falling clk;
  divclk <= clk&enb after 1ns;

  a  <= hi[2:0].lo[3] after 1ns;
  b  <= ~md when sub_add else md after 1 ns; // subtract or add
  adder use add4c(a, b, sub_add, sum, cout);  // note: cin == sub_add
  quo <= ~sum[3] after 1ns;

  hi      <= sum         on falling divclk after 1ns;
  lo      <= lo[2:0].quo on falling divclk after 1ns;
  sub_add <= quo         on falling divclk after 1ns;

end circuits;