-- dff_cntr2.vhdl   full D flip flop coded as nand gates, tested as counter

library IEEE;
use IEEE.std_logic_1164.all;

entity nand3 is -- a basic 3 input nand component
  port(in1, in2, in3 : in  std_logic;
       out1          : out std_logic);
end entity nand3;

architecture behaviour of nand3 is
begin
  out1 <= not(in1 and in2 and in3) after 1 ns;
end architecture behaviour; -- of nand3

library IEEE;
use IEEE.std_logic_1164.all;

entity dff is  -- D flip flop
  port(d     : in    std_logic;            -- input read on rising clock
       clk  : in    std_logic;             -- standard clock signal
       reset : in    std_logic;            -- normally high, low to reset
       set   : in    std_logic;            -- normally high, low to set
       q     : inout std_logic;            -- output
       q_bar : inout std_logic);           -- complement output
end entity dff;

architecture circuit of dff is
  signal d1, d1_bar, d2, d2_bar : std_logic; -- internal signals
  component nand3
    port(in1, in2, in3 : in  std_logic;
         out1          : out std_logic);
  end component nand3;
begin
  d1a: nand3 port map(d1_bar, set   , d2_bar, d1    );
  d1b: nand3 port map(d1    , reset , clk   , d1_bar);
  d2a: nand3 port map(d2_bar, d1_bar, clk   , d2    );
  d2b: nand3 port map(d2    , reset , d     , d2_bar);
  qa:  nand3 port map(q_bar , set   , d1_bar, q     );
  qb:  nand3 port map(q     , reset , d2    , q_bar );
end architecture circuit;  -- of dff

-- test circuit that makes a four bit counter out of D flip flops
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;

entity dff_cntr2 is   -- test bench
end entity dff_cntr2;

architecture circuit of dff_cntr2 is
  signal clk   : std_logic := '0';      -- system clock 
  signal reset : std_logic := '0';      -- reset signal to all D flip flops
  signal set   : std_logic := '1';      -- set   signal to all D flip flops
  signal d0, d1, d2, d3 : std_logic := '0';    -- D flip flop inputs
  signal clk1, clk2, clk3 : std_logic := '0';  -- D flip flop clocks
  signal q0, q1, q2, q3 : std_logic;    -- D flip flop outputs
  signal q0_bar, q1_bar, q2_bar, q3_bar : std_logic; -- complement outputs
  component dff
    port(d     : in    std_logic;            -- input read on rising clock
         clk   : in    std_logic;            -- standard clock signal
         reset : in    std_logic;            -- normally high, low to reset
         set   : in    std_logic;            -- normally high, low to set
         q     : inout std_logic;            -- output
         q_bar : inout std_logic);           -- complement output
  end component dff;
begin  -- circuit of dff_cntr2
  clk <= not clk after 16 ns;     -- control circuitry needs time
  reset <= '0', '1' after 4 ns;   -- one time reset based on start

  dff0: dff port map(d0, clk,  reset, set, q0, q0_bar);
  dff1: dff port map(d1, clk1, reset, set, q1, q1_bar);
  dff2: dff port map(d2, clk2, reset, set, q2, q2_bar);
  dff3: dff port map(d3, clk3, reset, set, q3, q3_bar);

  -- circuitry that makes a four bit counter out of D flip flops
  -- note the classic structure: state outputs through gates to state inputs
  d0 <= q0_bar after 1 ns;   -- clk transition 0 to 1
  d1 <= q1_bar after 1 ns;
  clk1 <= q0_bar after 2 ns; -- transition 0 to 1
  d2 <= q2_bar after 1 ns;
  clk2 <= q1_bar after 2 ns; -- transition 0 to 1
  d3 <= q3_bar after 1 ns;
  clk3 <= q2_bar after 2 ns; -- transition 0 to 1

  print: process (clk) is  -- show counting
    variable my_line : line;
  begin
    if clk='0' then
      write(my_line, string'("q3,q2,q1,q0="));
      write(my_line, q3);
      write(my_line, q2);
      write(my_line, q1);
      write(my_line, q0);
      write(my_line, string'(", at "));
      write(my_line, now);
      writeline(output, my_line);
    end if;
  end process print;
end architecture circuit;  -- of dff_cntr2