Memory bus to I/O operation Given a memory and an I/O device on a bus as shown below: 64 bit wide bus, synchronous, 200MHz clock ============================================================== | | address and | two 32-bit data address and | two 32-bit data word count | words sent word count | words received received in | in one clock sent in one | in one clock one clock | clock | | | +-----+-----+-----+-----+ +-----+-----+ | | | | | | I/O device| +-----+-----+-----+-----+ | receiving | | RAM memory that is | | word-count| | four 32-bit words wide| | words of | | and has output | | data | | registers for four | +-----------+ | words | +-----------------------+ The system operates by the I/O device sending an address and word count to the memory. The memory uses the address to start a memory access that brings four 32-bit words into the memory output registers. In parallel, [the memory starts the access of the next four words] and [sends two words on the bus, then two more words on the bus, then a bus idle, then another bus idle]. Note that the bus may be used by other devices between these four clock operations on the bus. The memory access is non uniform. Upon receiving an address, the first memory access takes longer than the following memory accesses. This happens in some memories due to the extra time to charge word or block select lines. Once started with an address and word count, the memory puts data on the bus until the word count is satisfied. For this example the first memory access requires 35 nanoseconds and each additional memory access requires 25 nanoseconds. A bus transaction starts with the sending of an address and word count. The transaction ends when the last word and two idles are received by the I/O device. The transaction time does not include the one clock to send the address and word count. Bandwidth is measured in megabytes per second. The address and word count are not included in the byte count and not included in the time. For the I/O device to get 64 words when the I/O device uses 8 as the word count. To compute the total time from receipt of the address to the end of the last transaction: Note that a 200MHz bus means 5ns per bus action. Thus 64 bits (2 words) can be sent every 5ns. In order to compute total time, this example works in nanoseconds (another method is to work in clock counts.) time action from to 0ns 5ns address and word count from I/O device to memory 5ns 40ns memory taking 35ns to perform fetch of four words 40ns 45ns two words go from memory to I/O device W0, W1 memory starts fetching next four words 45ns 50ns two words go from memory to I/O device W2, W3 memory still fetching next four words 50ns 55ns idle to bus memory still fetching next four words 55ns 60ns second idle to bus memory still fetching next four words 60ns 65ns memory finishes taking 25ns to fetch next four words 65ns 70ns two words go from memory to I/O device W4, W5 70ns 75ns two words go from memory to I/O device W6, W7 75ns 80ns idle to bus 80ns 85ns second idle to bus Not counting address, 80ns for transaction that sent 8 words. We need to send 64 words, thus there are 8 of these transactions. The total time is 8 * 80ns = 640ns for all 64 words. Since there were 8 transactions for an average of 640ns/8 = 80ns The number of transactions per second is 1/80*10^-9 = 12.5 million per second To get the bandwidth, compute the total number of bytes 64 words times 4 bytes per word = 256 bytes. MegaBytes per second is then (256bytes/640ns)/10^6 = 400 MB/sec