-- alu_start.vhdl

library IEEE;
use IEEE.std_logic_1164.all;

entity alu_32 is
  port(inA    : in  std_logic_vector (31 downto 0);
       inB    : in  std_logic_vector (31 downto 0);
       inst   : in  std_logic_vector (31 downto 0);
       result : out std_logic_vector (31 downto 0));
end entity alu_32;


architecture schematic of alu_32 is 
  signal cin     : std_logic := '0';
  signal cout    : std_logic;
begin  -- schematic
  --
  --   REPLACE THIS SECTION FOR PROJECT PART 1
  --   (add the signals you need above the "begin"
  --    add logic below the "begin")
  
  adder: entity WORK.add32 port map(a    => inA,
                                    b    => inB,     -- change
                                    cin  => cin,     -- change
                                    sum  => result,  -- change
                                    cout => cout);

-- examples of entity instantiations:
  
-- bsh: entity WORK.bshift port map (left    => sllop,
--                                   logical => '1',
--                                   shift   => inst(10 downto 6),
--                                   input   => inB,
--                                   output  => bresult);

-- r1: entity WORK.equal6  port map (inst  => inst(31 downto 26),
--                                   test  => "000000",
--                                   equal => rrop);
                                     
  
end architecture schematic;  -- of alu_32