-- test timing of adder stages
-- add_trace.vhdl    this could be three or more files

library IEEE;
use IEEE.std_logic_1164.all;

entity fadd is               -- full adder stage, interface
  port(a    : in  std_logic;
       b    : in  std_logic;
       cin  : in  std_logic;
       s    : out std_logic;
       cout : out std_logic);
end entity fadd;

architecture circuits of fadd is  -- full adder stage, body
begin  -- circuits of fadd
  s <= a xor b xor cin after 1 ns;
  cout <= (a and b) or (a and cin) or (b and cin) after 1 ns;
end architecture circuits; -- of fadd

use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;

entity add_trace is
end add_trace;

architecture circuits of add_trace is
  signal c:      std_logic_vector(3 downto 0);
  signal s:      std_logic_vector(3 downto 0);       
  signal a:      std_logic_vector(3 downto 0):=('0','0','0','1');
  signal b:      std_logic_vector(3 downto 0):=('1','1','1','1');
  signal cin :   std_logic := '0';
  
  type trace8 is array (1 to 8) of std_logic_vector(0 to 64);
  signal trace : trace8;
  type label8 is array (1 to 8) of string(1 to 6);
  signal labels : label8 := ("s(0)  ", "s(1)  ", "s(2)  ", "s(3)  ",
                             "c(0)  ", "c(1)  ", "c(2)  ", "c(3)  ");

  procedure print_values is       -- format output
    variable my_line : LINE;
  begin
    write(my_line, string'("s(0)="));
    write(my_line, s(0));
    write(my_line, string'(", s(1)="));
    write(my_line, s(1));
    write(my_line, string'(", s(2)="));
    write(my_line, s(2));
    write(my_line, string'(", s(3)="));
    write(my_line, s(3));
    write(my_line, string'(", c(0)="));
    write(my_line, c(0));
    write(my_line, string'(", c(1)="));
    write(my_line, c(1));
    write(my_line, string'(", c(2)="));
    write(my_line, c(2));
    write(my_line, string'(", c(3)="));
    write(my_line, c(3));
    write(my_line, string'(" at "));
    write(my_line, now);
    writeline(output, my_line);
  end print_values;


  procedure print_trace is
    variable my_line : LINE;
  begin
    writeline(output, my_line); -- blank line
    for j in 1 to 8 loop
      write(my_line, string'("      "));
      for i in 1 to 31 loop
        if trace(j)(i)='1' and trace(j)(i-1)='1' then
          write(my_line, '_');
        else
          write(my_line, ' ');
        end if;              
      end loop;  -- i            
      writeline(output, my_line);
      write(my_line, labels(j));
      for i in 1 to 31 loop
        if trace(j)(i)='U' then
          write(my_line, character' ('U'));
        elsif trace(j)(i)='X' then
          write(my_line, character' ('X'));
        elsif (trace(j)(i)='1' and trace(j)(i-1)='0') or
              (trace(j)(i)='0' and trace(j)(i-1)='1') then
          write(my_line, '|');
        elsif trace(j)(i)='0' then
          write(my_line, '_');
        else
          write(my_line, ' ');
        end if;
      end loop;  -- i
      writeline(output, my_line);
    end loop; -- j
    writeline(output, my_line); -- blank line
  end print_trace;
  
begin  -- circuits of add_trace
  a0: entity WORK.fadd port map(a(0), b(0),  cin, s(0), c(0));
  a1: entity WORK.fadd port map(a(1), b(1), c(0), s(1), c(1));
  a2: entity WORK.fadd port map(a(2), b(2), c(1), s(2), c(2));
  a3: entity WORK.fadd port map(a(3), b(3), c(2), s(3), c(3));

  driver: process                      -- serial code, test driver
            variable my_line : LINE;
          begin  -- process driver
            for i in 0 to 32 loop 
              wait for 250 ps;         --  propagating signals
              print_values;            -- write output
              trace(1)(i) <= s(0);
              trace(2)(i) <= s(1);
              trace(3)(i) <= s(2);
              trace(4)(i) <= s(3);
              trace(5)(i) <= c(0);
              trace(6)(i) <= c(1);
              trace(7)(i) <= c(2);
              trace(8)(i) <= c(3);
            end loop;  -- i
            print_trace;               -- print saved values
          end process driver;
end architecture circuits; -- of add_trace