-- add64.vhdl entities and package -- standard P,G design of circuits of add64 -- also included behavior of add64 library IEEE; use IEEE.std_logic_1164.all; entity add4pg is port(a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); cin : in std_logic; sum : out std_logic_vector(3 downto 0); p : out std_logic; g : out std_logic ); end entity add4pg ; architecture circuits of add4pg is signal c : std_logic_vector(2 downto 0); begin -- circuits of add4pg sum(0) <= a(0) xor b(0) xor cin after 1 ns; c(0) <= (a(0) and b(0)) or (a(0) and cin) or (b(0) and cin) after 1 ns; sum(1) <= a(1) xor b(1) xor c(0) after 1 ns; c(1) <= (a(1) and b(1)) or (a(1) and a(0) and b(0)) or (a(1) and a(0) and cin) or (a(1) and b(0) and cin) or (b(1) and a(0) and b(0)) or (b(1) and a(0) and cin) or (b(1) and b(0) and cin) after 1 ns; sum(2) <= a(2) xor b(2) xor c(1) after 1 ns; c(2) <= (a(2) and b(2)) or (a(2) and c(1)) or (b(2) and c(1)) after 1 ns; sum(3) <= a(3) xor b(3) xor c(2) after 1 ns; p <= (a(0) or b(0)) and (a(1) or b(1)) and (a(2) or b(2)) and (a(3) or b(3)) after 1 ns; g <= (a(3) and b(3)) or ((a(3) or b(3)) and ((a(2) and b(2)) or ((a(2) or b(2)) and ((a(1) and b(1)) or ((a(1) or b(1)) and ((a(0) and b(0)))))))) after 1 ns; end architecture circuits; -- of add4pg library IEEE; use IEEE.std_logic_1164.all; entity pg4a is port(p0 : in std_logic; p1 : in std_logic; p2 : in std_logic; p3 : in std_logic; g0 : in std_logic; g1 : in std_logic; g2 : in std_logic; g3 : in std_logic; cin : in std_logic; pout : out std_logic; gout : out std_logic; c1 : out std_logic; c2 : out std_logic; c3 : out std_logic); end entity pg4a ; architecture circuits of pg4a is begin -- circuits of pg4a c1 <= g0 or (p0 and cin) after 1 ns; c2 <= g1 or (p1 and g0) or (p1 and p0 and cin) after 1 ns; c3 <= g2 or (p2 and g1) or (p2 and p1 and g0) or (p2 and p1 and p0 and cin) after 1 ns; pout <= p0 and p1 and p2 and p3 after 1 ns; gout <= g3 or (p3 and g2) or (p3 and p2 and g1) or (p3 and p2 and p1 and g0) after 1 ns; end architecture circuits; -- of pg4a library IEEE; use IEEE.std_logic_1164.all; entity pg4b is port(p0 : in std_logic; p1 : in std_logic; p2 : in std_logic; p3 : in std_logic; g0 : in std_logic; g1 : in std_logic; g2 : in std_logic; g3 : in std_logic; cin : in std_logic; c1 : out std_logic; c2 : out std_logic; c3 : out std_logic; cout : out std_logic); end entity pg4b ; architecture circuits of pg4b is begin -- circuits of pg4b c1 <= g0 or (p0 and cin) after 1 ns; c2 <= g1 or (p1 and g0) or (p1 and p0 and cin) after 1 ns; c3 <= g2 or (p2 and g1) or (p2 and p1 and g0) or (p2 and p1 and p0 and cin) after 1 ns; cout <= g3 or (p3 and g2) or (p3 and p2 and g1) or (p3 and p2 and p1 and g0) or (p3 and p2 and p1 and p0 and cin) after 1 ns; end architecture circuits; -- of pg4b library IEEE; use IEEE.std_logic_1164.all; entity add64 is port(a : in std_logic_vector(63 downto 0); b : in std_logic_vector(63 downto 0); cin : in std_logic; sum : out std_logic_vector(63 downto 0); cout : out std_logic); end entity add64; architecture circuits of add64 is signal c1, c2, c3, c4, c5, c6, c7: std_logic; -- internal carry signals signal c8, c9, c10, c11, c12, c13, c14, c15: std_logic; signal p0, p1, p2, p3, p4, p5, p6, p7: std_logic; -- internal propagate signal p8, p9, p10, p11, p12, p13, p14, p15: std_logic; signal g0, g1, g2, g3, g4, g5, g6, g7: std_logic; -- internal generate signal g8, g9, g10, g11, g12, g13, g14, g15: std_logic; signal pn0, pn1, pn2, pn3 : std_logic; signal gn0, gn1, gn2, gn3 : std_logic; component add4pg -- duplicates entity port port(a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); cin : in std_logic; sum : out std_logic_vector(3 downto 0); p : out std_logic; g : out std_logic); end component add4pg ; component pg4a -- duplicates entity port port(p0 : in std_logic; p1 : in std_logic; p2 : in std_logic; p3 : in std_logic; g0 : in std_logic; g1 : in std_logic; g2 : in std_logic; g3 : in std_logic; cin : in std_logic; pout : out std_logic; gout : out std_logic; c1 : out std_logic; c2 : out std_logic; c3 : out std_logic); end component pg4a; component pg4b -- duplicates entity port port(p0 : in std_logic; p1 : in std_logic; p2 : in std_logic; p3 : in std_logic; g0 : in std_logic; g1 : in std_logic; g2 : in std_logic; g3 : in std_logic; cin : in std_logic; c1 : out std_logic; c2 : out std_logic; c3 : out std_logic; cout : out std_logic); end component pg4b; begin -- circuits of add64 a0: add4pg port map(a( 3 downto 0), b( 3 downto 0), cin, sum( 3 downto 0), p0, g0); a1: add4pg port map(a( 7 downto 4), b( 7 downto 4), c1 , sum( 7 downto 4), p1, g1); a2: add4pg port map(a(11 downto 8), b(11 downto 8), c2 , sum(11 downto 8), p2, g2); a3: add4pg port map(a(15 downto 12), b(15 downto 12), c3 , sum(15 downto 12), p3, g3); pg00: pg4a port map(p0, p1, p2, p3, g0, g1, g2, g3, cin, pn0, gn0, c1, c2, c3); a4: add4pg port map(a(19 downto 16), b(19 downto 16), c4 , sum(19 downto 16), p4, g4); a5: add4pg port map(a(23 downto 20), b(23 downto 20), c5 , sum(23 downto 20), p5, g5); a6: add4pg port map(a(27 downto 24), b(27 downto 24), c6 , sum(27 downto 24), p6, g6); a7: add4pg port map(a(31 downto 28), b(31 downto 28), c7 , sum(31 downto 28), p7, g7); pg01: pg4a port map(p4, p5, p6, p7, g4, g5, g6, g7, c4, pn1, gn1, c5, c6, c7); a8: add4pg port map(a(35 downto 32), b(35 downto 32), c8 , sum(35 downto 32), p8, g8); a9: add4pg port map(a(39 downto 36), b(39 downto 36), c9 , sum(39 downto 36), p9, g9); a10:add4pg port map(a(43 downto 40), b(43 downto 40), c10, sum(43 downto 40), p10, g10); a11:add4pg port map(a(47 downto 44), b(47 downto 44), c11, sum(47 downto 44), p11, g11); pg02: pg4a port map(p8, p9, p10, p11, g8, g9, g10, g11, c8, pn2, gn2, c9, c10, c11); a12:add4pg port map(a(51 downto 48), b(51 downto 48), c12, sum(51 downto 48), p12, g12); a13:add4pg port map(a(55 downto 52), b(55 downto 52), c13, sum(55 downto 52), p13, g13); a14:add4pg port map(a(59 downto 56), b(59 downto 56), c14, sum(59 downto 56), p14, g14); a15:add4pg port map(a(63 downto 60), b(63 downto 60), c15, sum(63 downto 60), p15, g15); pg03: pg4a port map(p12, p13, p14, p15, g12, g13, g14, g15, c12, pn3, gn3, c13, c14, c15); pg04: pg4b port map(pn0, pn1, pn2, pn3, gn0, gn1, gn2, gn3, cin, c4, c8, c12, cout); end architecture circuits; -- of add64 library IEEE; -- now a behavior, code, architecture use IEEE.std_logic_arith.all; architecture behavior of add64 is signal temp : std_logic_vector(64 downto 0); signal vcin : std_logic_vector(64 downto 0) := X"0000000000000000"&b"0"; signal va : std_logic_vector(64 downto 0) := X"0000000000000000"&b"0"; signal vb : std_logic_vector(64 downto 0) := X"0000000000000000"&b"0"; begin -- behavior of add64 vcin(0) <= cin; va(63 downto 0) <= a; vb(63 downto 0) <= b; temp <= unsigned(va) + unsigned(vb) + unsigned(vcin); cout <= temp(64); sum <= temp(63 downto 0); end architecture behavior; -- of add64