-- add4.vhdl     entities and architectures
--               fadd   a one bit adder
--               add4   a simple 4 bit adder with fast cout generation

library IEEE;
use IEEE.std_logic_1164.all;

entity fadd is                          -- simple one stage adder
  port(a    : in  std_logic;
       b    : in  std_logic;
       cin  : in  std_logic;
       s    : out std_logic;
       cout : out std_logic);
end entity fadd;

architecture circuits of fadd is
begin  -- circuits of fadd
  s <= a xor b xor cin after 10 ps;
  cout <= (a and b) or (a and cin) or (b and cin) after 10 ps;
end architecture circuits; -- of fadd


-- add4    4 bit full adder component
-- simple ripple carry adder with fast cout
-- inputs a, b, cin
-- outputs sum, cout

library IEEE;
use IEEE.std_logic_1164.all;
entity add4 is
  port(a    : in  std_logic_vector(3 downto 0);
       b    : in  std_logic_vector(3 downto 0);
       cin  : in  std_logic; 
       sum  : out std_logic_vector(3 downto 0);
       cout : out std_logic);
end entity add4 ;

architecture circuits of add4 is
  signal c : std_logic_vector(3 downto 0);
  component fadd    -- duplicates entity port
    port(a    : in  std_logic;
         b    : in  std_logic;
         cin  : in  std_logic;
         s    : out std_logic;
         cout : out std_logic);
  end component fadd;
begin  -- circuits of add4
  a0: fadd port map(a(0), b(0), cin , sum(0), c(0));
  a1: fadd port map(a(1), b(1), c(0), sum(1), c(1));
  a2: fadd port map(a(2), b(2), c(1), sum(2), c(2));
  a3: fadd port map(a(3), b(3), c(2), sum(3), c(3));
  cout <= (a(3) and b(3)) or ((a(3) or b(3)) and
         ((a(2) and b(2)) or ((a(2) or b(2)) and
         ((a(1) and b(1)) or ((a(1) or b(1)) and
         ((a(0) and b(0)) or ((a(0) or b(0)) and cin)))))))
         after 20 ps;
end architecture circuits;  -- of add4


-- add32   a simple 32 bit adder with fast cout generation
--         this uses the components, above,  fadd  add4 
-- library IEEE;
-- use IEEE.std_logic_1164.all;
--
-- entity add32 is
--   port(a    : in  std_logic_vector(31 downto 0);
--        b    : in  std_logic_vector(31 downto 0);
--        cin  : in  std_logic; 
--        sum  : out std_logic_vector(31 downto 0);
--        cout : out std_logic);
-- end entity add32;