-- add32pg.vhdl    entities and architectures
--                 standard P,G design of  circuits of add32
--                 also included  behavior of add32

library IEEE;
use IEEE.std_logic_1164.all;
entity add4pg is
  port(a    : in  std_logic_vector(3 downto 0);
       b    : in  std_logic_vector(3 downto 0);
       cin  : in  std_logic; 
       sum  : out std_logic_vector(3 downto 0);
       p    : out std_logic;
       g    : out std_logic );
end entity add4pg ;

architecture circuits of add4pg is
  signal c : std_logic_vector(2 downto 0);
begin  -- circuits of add4pg
  sum(0) <= a(0) xor b(0) xor cin after 2 ps;
  c(0)   <= (a(0) and b(0)) or (a(0) and cin) or (b(0) and cin) after 2 ps;
  sum(1) <= a(1) xor b(1) xor c(0) after 2 ps;
  c(1)   <= (a(1) and b(1)) or
            (a(1) and a(0) and b(0)) or
            (a(1) and a(0) and cin)  or
            (a(1) and b(0) and cin)  or
            (b(1) and a(0) and b(0)) or
            (b(1) and a(0) and cin)  or
            (b(1) and b(0) and cin) after 2 ps;
  sum(2) <= a(2) xor b(2) xor c(1) after 2 ps;
  c(2)   <= (a(2) and b(2)) or (a(2) and c(1)) or (b(2) and c(1)) after 2 ps;
  sum(3) <= a(3) xor b(3) xor c(2) after 2 ps;
  p      <= (a(0) or b(0)) and (a(1) or b(1)) and
            (a(2) or b(2)) and (a(3) or b(3)) after 2 ps;
  g      <= (a(3) and b(3)) or ((a(3) or b(3)) and
            ((a(2) and b(2)) or ((a(2) or b(2)) and
            ((a(1) and b(1)) or ((a(1) or b(1)) and
            ((a(0) and b(0)))))))) after 2 ps;
end architecture circuits;  -- of add4pg

library IEEE;
use IEEE.std_logic_1164.all;
entity pg3 is 
  port(p0   : in  std_logic;
       p1   : in  std_logic;
       p2   : in  std_logic; 
       p3   : in  std_logic;
       g0   : in  std_logic;
       g1   : in  std_logic;
       g2   : in  std_logic; 
       g3   : in  std_logic;
       cin  : in  std_logic;
       pout : out std_logic;
       gout : out std_logic;
       c1   : out std_logic;
       c2   : out std_logic;
       c3   : out std_logic);
end entity pg3 ;

architecture circuits of pg3 is
begin  -- circuits of pg3
  c1   <= g0 or (p0 and cin) after 2 ps;
  c2   <= g1 or (p1 and g0) or (p1 and p0 and cin) after 2 ps;
  c3   <= g2 or (p2 and g1) or (p2 and p1 and g0) or
          (p2 and p1 and p0 and cin) after 2 ps;
  pout <= p0 and p1 and p2 and p3 after 2 ps;
  gout <= g3 or
          (p3 and g2) or
          (p3 and p2 and g1) or
          (p3 and p2 and p1 and g0) after 2 ps;
end architecture circuits;  -- of pg3


library IEEE;
use IEEE.std_logic_1164.all;
entity pg4 is
  port(p0   : in  std_logic;
       p1   : in  std_logic;
       g0   : in  std_logic;
       g1   : in  std_logic;
       cin  : in  std_logic;
       c1   : out std_logic;
       c2   : out std_logic;
       cout : out std_logic);
end entity pg4 ;

architecture circuits of pg4 is
begin  -- circuits of pg4
  c1   <= g0 or
          (p0 and cin) after 2 ps;
  c2   <= g1 or
          (p1 and g0) or
          (p1 and p0 and cin) after 2 ps;
  cout <= g1 or
          (p1 and g0) or
          (p1 and p0 and cin) after 2 ps;
end architecture circuits;  -- of pg4

library IEEE;
use IEEE.std_logic_1164.all;
entity add32 is
  port(a    : in  std_logic_vector(31 downto 0);
       b    : in  std_logic_vector(31 downto 0);
       cin  : in  std_logic; 
       sum  : out std_logic_vector(31 downto 0);
       cout : out std_logic);
end entity add32;

architecture circuits of add32 is
  signal c1, c2, c3, c4, c5, c6, c7: std_logic; -- internal carry signals
  signal p0, p1, p2, p3, p4, p5, p6, p7: std_logic; -- internal propagate
  signal g0, g1, g2, g3, g4, g5, g6, g7: std_logic; -- internal generate
  signal pn0, pn1: std_logic;
  signal gn0, gn1: std_logic;
begin  -- circuits of add32
 a0: entity work.add4pg port map(a( 3 downto  0), b( 3 downto  0), cin,
                                 sum( 3 downto  0), p0, g0);
 a1: entity work.add4pg port map(a( 7 downto  4), b( 7 downto  4), c1 ,
                                 sum( 7 downto  4), p1, g1);
 a2: entity work.add4pg port map(a(11 downto  8), b(11 downto  8), c2 ,
                                 sum(11 downto  8), p2, g2);
 a3: entity work.add4pg port map(a(15 downto 12), b(15 downto 12), c3 ,
                                 sum(15 downto 12), p3, g3);
 pg00: entity work.pg3 port map(p0, p1, p2, p3, g0, g1, g2, g3, cin,
                                pn0, gn0, c1, c2, c3);
 
 a4: entity work.add4pg port map(a(19 downto 16), b(19 downto 16), c4 ,
                                 sum(19 downto 16), p4, g4);
 a5: entity work.add4pg port map(a(23 downto 20), b(23 downto 20), c5 ,
                                 sum(23 downto 20), p5, g5);
 a6: entity work.add4pg port map(a(27 downto 24), b(27 downto 24), c6 ,
                                 sum(27 downto 24), p6, g6);
 a7: entity work.add4pg port map(a(31 downto 28), b(31 downto 28), c7 ,
                                 sum(31 downto 28), p7, g7);
 pg01: entity work.pg3 port map(p4, p5, p6, p7, g4, g5, g6, g7, c4,
                                pn1, gn1, c5, c6, c7);

 -- a8 through a15, pg02, pg03 needed for 64-bit adder
 
 pg04: entity work.pg4 port map(pn0, pn1, gn0, gn1, cin, c4, cout);

end architecture circuits;  -- of add32

-- OR REPLACE all above except   library ... entity add32 ... end entity add32;
-- and use the behavioral model below

library IEEE;
use IEEE.std_logic_arith.all;
architecture behavior of add32 is
  signal temp : std_logic_vector(32 downto 0);
  signal vcin : std_logic_vector(32 downto 0) := X"00000000"&'0';
  signal va   : std_logic_vector(32 downto 0) := X"00000000"&'0';
  signal vb   : std_logic_vector(32 downto 0) := X"00000000"&'0';
  -- 33 bits (32 downto 0) needed to compute cout
begin  -- circuits of add32
  vcin(0) <= cin;
  va(31 downto 0) <= a;
  vb(31 downto 0) <= b;
  temp <= unsigned(va) + unsigned(vb) + unsigned(vcin);
  cout <= temp(32) after 6 ps;
  sum  <= temp(31 downto 0) after 6 ps;
end architecture behavior;  -- of add32