-- add32_test_b.vhdl   test add32(behavior)

library STD;
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;

entity add32_test_b is                 -- test bench for add32(behavior)
end add32_test_b;

architecture circuits of add32_test_b is
  signal cntr: std_logic_vector(4 downto 0) := b"00000";
  signal a:    std_logic_vector(31 downto 0) := x"00000000";
                                      -- initial value of 32 bits of zero
  signal b:    std_logic_vector(31 downto 0) := x"FFFFFFFF";
                                      -- initial 32 bit hexadecimal value    
  signal cin:  std_logic := '1';
  signal cout: std_logic;            
  signal sum:  std_logic_vector(31 downto 0);
  signal co2:  std_logic;             -- test with a and b interchanged
  signal s2:   std_logic_vector(31 downto 0);
                                      -- to be sure circuit is symmetric
  procedure my_printout(a:    std_logic_vector(31 downto 0);
                        b:    std_logic_vector(31 downto 0);
                        cin:  std_logic;
                        sum:  std_logic_vector(31 downto 0);
                        cout: std_logic;            
                        s2:   std_logic_vector(31 downto 0);
                        co2:  std_logic) is
    variable my_line : LINE;
    alias swrite is write [line, string, side, width] ;
  begin
    swrite(my_line, "    a=");
    hwrite(my_line, a);
    swrite(my_line, ",    b=");
    hwrite(my_line, b);
    swrite(my_line, ",  cin=");
    write(my_line, cin);
    writeline(output, my_line);
    swrite(my_line, "  sum=");
    hwrite(my_line, sum);
    swrite(my_line, ", cout=");
    write(my_line, cout);
    swrite(my_line, ",   s2=");
    hwrite(my_line, s2);
    swrite(my_line, ",  co2=");
    write(my_line, co2);
    swrite(my_line, ", cntr=");
    write(my_line, cntr);
    swrite(my_line, ",  at=");
    write(my_line, now);
    writeline(output, my_line);
    writeline(output, my_line); -- blank line
  end my_printout;
  
begin  -- circuits of add32_test_b
  adder: entity work.add32(behavior)
         port map(a, b, cin, sum, cout); -- parallel circuit
  addrv: entity work.add32(behavior)
         port map(b, a, cin, s2,  co2);  -- parallel circuit
         cntr <= unsigned(cntr) + unsigned'(b"00001") after 40 ns;
                                                -- increment counter
  driver: process                               -- serial code
            variable my_line : LINE;
          begin  -- process driver
            write(my_line, string'("Driver starting."));
            writeline(output, my_line);
            
            for i in 0 to 31 loop  -- 32 test cases
              cin   <= cntr(0) after 1 ns;
              a(0)  <= cntr(1) after 1 ns;
              a(4)  <= cntr(2) after 1 ns;
              a(8)  <= cntr(3) after 1 ns;
              a(28) <= cntr(4) after 1 ns;
              wait for 20 ns;           -- adders propagating signals
              my_printout(a, b, cin, sum, cout, s2, co2);  -- write output
              wait for 20 ns;           -- other half of clock cycle
            end loop;  -- i
          end process driver;
end architecture circuits; -- of add32_test_b