// add16.e   set of components to build a 16 bit carry PG adder

// fadd.e  1 bit full adder component for  esim  use

// 1 bit stage of a full adder
define fadd(a, b, cin, s, cout)
circuits
  s <= a ^ b ^ cin after 1ns;
  cout <= (a&b)|(a&cin)|(b&cin) after 1ns;
end circuits;
end fadd;

// add4pg.e  4 bits of adder that outputs P and G

// 4 bit stage with 9 inputs and 6 outputs
define add4pg(a[4], b[4], cin, s[4], P, G)
signal c0, c1, c2;
signal nc1;
circuits
  // basic four stages
  s00 use fadd(a[0], b[0], cin, s[0], c0);
  s01 use fadd(a[1], b[1], c0,  s[1], c1);
  s02 use fadd(a[2], b[2], c1,  s[2], c2);
  s03 use fadd(a[3], b[3], c2,  s[3], nc1);

  // Propegate and Generate terms and outputs 
  P <= (a[0]|b[0])&(a[1]|b[1])&(a[2]|b[2])&(a[3]|b[3]) after 1ns;
  G <= (a[3]&b[3])|((a[3]|b[3])&((a[2]&b[2])|((a[2]|b[2])&((a[1]&b[1])|
       ((a[1]|b[1])&((a[0]&b[0])|(a[0]|b[0])&cin)))))) after 1ns;
end circuits;
end add4pg;

// carryla.e  Use P and G to generate carry in for four stages

define carryla(p[4], g[4], cin,  c[3], cout)
circuits
  c[0] <= g[0]|(p[0]&cin) after 1ns;
  c[1] <= g[1]|(p[1]&g[0])|(p[1]&p[0]&cin) after 1ns;
  c[2] <= g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&cin) after 1ns;
  cout <= g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|
          (p[3]&p[2]&p[1]&p[0]&cin) after 1ns;
end circuits;
end carryla;


// add16.e   4 four bit stages and carry look ahead

define add16(a[16], b[16], cin, s[16], cout)
signal pout[4];
signal gout[4];
signal c[3];
circuits
  a0 use add4pg(a[3:0],   b[3:0],   cin,  s[3:0],   pout[0], gout[0]);
  a1 use add4pg(a[7:4],   b[7:4],   c[0], s[7:4],   pout[1], gout[1]);
  a2 use add4pg(a[11:8],  b[11:8],  c[1], s[11:8],  pout[2], gout[2]);
  a3 use add4pg(a[15:12], b[15:12], c[2], s[15:12], pout[3], gout[3]);
  pg use carryla(pout, gout, cin, c, cout);
end circuits;
end add16;